glibc/sysdeps/x86
H.J. Lu ea8e465a6b x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
From

https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

* Intel TSX will be disabled by default.
* The processor will force abort all Restricted Transactional Memory (RTM)
  transactions by default.
* A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
  which is set to indicate to updated software that the loaded microcode is
  forcing RTM abort.
* On processors that enumerate support for RTM, the CPUID enumeration bits
  for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
  be set by default after microcode update.
* Workloads that were benefited from Intel TSX might experience a change
  in performance.
* System software may use a new bit in Model-Specific Register (MSR) 0x10F
  TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
  Elision (HLE) and RTM bits to indicate to software that Intel TSX is
  disabled.

1. Add RTM_ALWAYS_ABORT to CPUID features.
2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.  This skips the
string/tst-memchr-rtm etc. testcases on the affected processors, which
always fail after a microcde update.
3. Check RTM feature, instead of usability, against /proc/cpuinfo.

This fixes BZ #28033.
2021-07-01 10:47:35 -07:00
..
bits x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] 2021-07-01 10:47:35 -07:00
fpu
include x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] 2021-07-01 10:47:35 -07:00
nptl nptl: Remove longjmp, siglongjmp from libpthread 2021-04-21 19:49:50 +02:00
sys/platform <sys/platform/x86.h>: Remove the C preprocessor magic 2021-01-21 05:58:17 -08:00
__longjmp_cancel.S
abi-note.c
atomic-machine.h
cacheinfo.c x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] 2021-03-15 05:43:26 -07:00
cacheinfo.h x86: Remove unused variables for raw cache sizes from cacheinfo.h 2021-02-22 17:36:03 +01:00
cet-control.h
check-cet.awk
configure x86: Set minimum x86-64 level marker [BZ #27318] 2021-03-06 07:49:30 -08:00
configure.ac x86: Set minimum x86-64 level marker [BZ #27318] 2021-03-06 07:49:30 -08:00
cpu-features-offsets.sym
cpu-features.c x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] 2021-07-01 10:47:35 -07:00
cpu-tunables.c x86: Set Prefer_No_VZEROUPPER and add Prefer_AVX2_STRCMP 2021-03-29 07:40:17 -07:00
dl-cacheinfo.h x86: Set rep_movsb_threshold to 2112 on processors with FSRM 2021-05-03 05:08:22 -07:00
dl-cet.c x86: Properly set usable CET feature bits [BZ #26625] 2021-01-29 03:58:11 -08:00
dl-diagnostics-cpu.c x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] 2021-03-15 05:43:26 -07:00
dl-get-cpu-features.c Fix misplaced const 2021-01-25 15:09:02 +01:00
dl-hwcap.h
dl-isa-level.h
dl-lookupcfg.h
dl-minsigstacksize.h sysconf: Add _SC_MINSIGSTKSZ/_SC_SIGSTKSZ [BZ #20305] 2021-02-01 11:00:52 -08:00
dl-procinfo.c
dl-procinfo.h
dl-procruntime.c
dl-prop.h
dl-tunables.list
elf-initfini.h
elide.h
float128-abi.h Move __isnanf128 to libc.so 2021-03-30 14:58:19 +05:30
fpu_control.h
get-cpuid-feature-leaf.c <sys/platform/x86.h>: Remove the C preprocessor magic 2021-01-21 05:58:17 -08:00
get-isa-level.h <sys/platform/x86.h>: Remove the C preprocessor magic 2021-01-21 05:58:17 -08:00
hp-timing.h
init-arch.h
isa-level.c x86: Set minimum x86-64 level marker [BZ #27318] 2021-03-06 07:49:30 -08:00
jmp_buf-ssp.sym
ldbl2mpn.c
ldsodefs.h
libc-start.c Use hidden visibility for early static PIE code 2021-01-21 15:55:01 +00:00
libc-start.h
link_map.h
linkmap.h
longjmp.c
Makeconfig
Makefile dlfcn: Cleanups after -ldl is no longer required 2021-06-03 09:11:45 +02:00
string_private.h
sysdep.h
tininess.h
tst-cet-legacy-1.c
tst-cet-legacy-1a.c
tst-cet-legacy-2.c
tst-cet-legacy-2a.c
tst-cet-legacy-3.c
tst-cet-legacy-4.c
tst-cet-legacy-4a.c
tst-cet-legacy-4b.c
tst-cet-legacy-4c.c
tst-cet-legacy-5.c x86: Properly set usable CET feature bits [BZ #26625] 2021-01-29 03:58:11 -08:00
tst-cet-legacy-5a.c
tst-cet-legacy-5b.c
tst-cet-legacy-6.c x86: Properly set usable CET feature bits [BZ #26625] 2021-01-29 03:58:11 -08:00
tst-cet-legacy-6a.c
tst-cet-legacy-6b.c
tst-cet-legacy-7.c
tst-cet-legacy-8.c
tst-cet-legacy-9-static.c x86: Properly set usable CET feature bits [BZ #26625] 2021-01-29 03:58:11 -08:00
tst-cet-legacy-9.c x86: Properly set usable CET feature bits [BZ #26625] 2021-01-29 03:58:11 -08:00
tst-cet-legacy-10-static.c x86: Properly set usable CET feature bits [BZ #26625] 2021-01-29 03:58:11 -08:00
tst-cet-legacy-10.c x86: Properly set usable CET feature bits [BZ #26625] 2021-01-29 03:58:11 -08:00
tst-cet-legacy-mod-1.c
tst-cet-legacy-mod-2.c
tst-cet-legacy-mod-4.c
tst-cet-legacy-mod-5.c
tst-cet-legacy-mod-5a.c
tst-cet-legacy-mod-5b.c
tst-cet-legacy-mod-5c.c
tst-cet-legacy-mod-6.c
tst-cet-legacy-mod-6a.c
tst-cet-legacy-mod-6b.c
tst-cet-legacy-mod-6c.c
tst-cet-legacy-mod-6d.c
tst-cpu-features-cpuinfo-static.c x86: Add PTWRITE feature detection [BZ #27346] 2021-02-07 08:01:14 -08:00
tst-cpu-features-cpuinfo.c x86: Fix tst-cpu-features-cpuinfo on Ryzen 9 (BZ #27873) 2021-06-24 09:57:46 -03:00
tst-cpu-features-supports-static.c x86: Add PTWRITE feature detection [BZ #27346] 2021-02-07 08:01:14 -08:00
tst-cpu-features-supports.c x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] 2021-07-01 10:47:35 -07:00
tst-get-cpu-features-static.c
tst-get-cpu-features.c x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] 2021-07-01 10:47:35 -07:00
tst-ifunc-isa-1-static.c x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072] 2021-01-21 10:22:26 -08:00
tst-ifunc-isa-1.c x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072] 2021-01-21 10:22:26 -08:00
tst-ifunc-isa-2-static.c x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072] 2021-01-21 10:22:26 -08:00
tst-ifunc-isa-2.c x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072] 2021-01-21 10:22:26 -08:00
tst-ifunc-isa.h Build get-cpuid-feature-leaf.c without stack-protector [BZ #27555] 2021-03-15 20:24:45 +05:30
tst-isa-level-1.c <sys/platform/x86.h>: Remove the C preprocessor magic 2021-01-21 05:58:17 -08:00
tst-isa-level-mod-1-baseline.c
tst-isa-level-mod-1-v2.c
tst-isa-level-mod-1-v3.c
tst-isa-level-mod-1-v4.c
tst-isa-level-mod-1.c
tst-ldbl-nonnormal-printf.c
tst-memchr-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-memcmp-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-memmove-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-memrchr-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-memset-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-setjmp-cet.c
tst-stack-align.h Properly check stack alignment [BZ #27901] 2021-05-24 07:42:12 -07:00
tst-strchr-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-strcpy-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-string-rtm.h x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-strlen-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-strncmp-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-strrchr-rtm.c x86: Add string/memory function tests in RTM region 2021-03-29 07:40:17 -07:00
tst-sysconf-cache-linesize-static.c x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] 2021-03-15 05:43:26 -07:00
tst-sysconf-cache-linesize.c x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] 2021-03-15 05:43:26 -07:00
Versions <sys/platform/x86.h>: Remove the C preprocessor magic 2021-01-21 05:58:17 -08:00