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From https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html * Intel TSX will be disabled by default. * The processor will force abort all Restricted Transactional Memory (RTM) transactions by default. * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated, which is set to indicate to updated software that the loaded microcode is forcing RTM abort. * On processors that enumerate support for RTM, the CPUID enumeration bits for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to be set by default after microcode update. * Workloads that were benefited from Intel TSX might experience a change in performance. * System software may use a new bit in Model-Specific Register (MSR) 0x10F TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock Elision (HLE) and RTM bits to indicate to software that Intel TSX is disabled. 1. Add RTM_ALWAYS_ABORT to CPUID features. 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the string/tst-memchr-rtm etc. testcases on the affected processors, which always fail after a microcde update. 3. Check RTM feature, instead of usability, against /proc/cpuinfo. This fixes BZ #28033. |
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.. | ||
bits | ||
fpu | ||
include | ||
nptl | ||
sys/platform | ||
__longjmp_cancel.S | ||
abi-note.c | ||
atomic-machine.h | ||
cacheinfo.c | ||
cacheinfo.h | ||
cet-control.h | ||
check-cet.awk | ||
configure | ||
configure.ac | ||
cpu-features-offsets.sym | ||
cpu-features.c | ||
cpu-tunables.c | ||
dl-cacheinfo.h | ||
dl-cet.c | ||
dl-diagnostics-cpu.c | ||
dl-get-cpu-features.c | ||
dl-hwcap.h | ||
dl-isa-level.h | ||
dl-lookupcfg.h | ||
dl-minsigstacksize.h | ||
dl-procinfo.c | ||
dl-procinfo.h | ||
dl-procruntime.c | ||
dl-prop.h | ||
dl-tunables.list | ||
elf-initfini.h | ||
elide.h | ||
float128-abi.h | ||
fpu_control.h | ||
get-cpuid-feature-leaf.c | ||
get-isa-level.h | ||
hp-timing.h | ||
init-arch.h | ||
isa-level.c | ||
jmp_buf-ssp.sym | ||
ldbl2mpn.c | ||
ldsodefs.h | ||
libc-start.c | ||
libc-start.h | ||
link_map.h | ||
linkmap.h | ||
longjmp.c | ||
Makeconfig | ||
Makefile | ||
string_private.h | ||
sysdep.h | ||
tininess.h | ||
tst-cet-legacy-1.c | ||
tst-cet-legacy-1a.c | ||
tst-cet-legacy-2.c | ||
tst-cet-legacy-2a.c | ||
tst-cet-legacy-3.c | ||
tst-cet-legacy-4.c | ||
tst-cet-legacy-4a.c | ||
tst-cet-legacy-4b.c | ||
tst-cet-legacy-4c.c | ||
tst-cet-legacy-5.c | ||
tst-cet-legacy-5a.c | ||
tst-cet-legacy-5b.c | ||
tst-cet-legacy-6.c | ||
tst-cet-legacy-6a.c | ||
tst-cet-legacy-6b.c | ||
tst-cet-legacy-7.c | ||
tst-cet-legacy-8.c | ||
tst-cet-legacy-9-static.c | ||
tst-cet-legacy-9.c | ||
tst-cet-legacy-10-static.c | ||
tst-cet-legacy-10.c | ||
tst-cet-legacy-mod-1.c | ||
tst-cet-legacy-mod-2.c | ||
tst-cet-legacy-mod-4.c | ||
tst-cet-legacy-mod-5.c | ||
tst-cet-legacy-mod-5a.c | ||
tst-cet-legacy-mod-5b.c | ||
tst-cet-legacy-mod-5c.c | ||
tst-cet-legacy-mod-6.c | ||
tst-cet-legacy-mod-6a.c | ||
tst-cet-legacy-mod-6b.c | ||
tst-cet-legacy-mod-6c.c | ||
tst-cet-legacy-mod-6d.c | ||
tst-cpu-features-cpuinfo-static.c | ||
tst-cpu-features-cpuinfo.c | ||
tst-cpu-features-supports-static.c | ||
tst-cpu-features-supports.c | ||
tst-get-cpu-features-static.c | ||
tst-get-cpu-features.c | ||
tst-ifunc-isa-1-static.c | ||
tst-ifunc-isa-1.c | ||
tst-ifunc-isa-2-static.c | ||
tst-ifunc-isa-2.c | ||
tst-ifunc-isa.h | ||
tst-isa-level-1.c | ||
tst-isa-level-mod-1-baseline.c | ||
tst-isa-level-mod-1-v2.c | ||
tst-isa-level-mod-1-v3.c | ||
tst-isa-level-mod-1-v4.c | ||
tst-isa-level-mod-1.c | ||
tst-ldbl-nonnormal-printf.c | ||
tst-memchr-rtm.c | ||
tst-memcmp-rtm.c | ||
tst-memmove-rtm.c | ||
tst-memrchr-rtm.c | ||
tst-memset-rtm.c | ||
tst-setjmp-cet.c | ||
tst-stack-align.h | ||
tst-strchr-rtm.c | ||
tst-strcpy-rtm.c | ||
tst-string-rtm.h | ||
tst-strlen-rtm.c | ||
tst-strncmp-rtm.c | ||
tst-strrchr-rtm.c | ||
tst-sysconf-cache-linesize-static.c | ||
tst-sysconf-cache-linesize.c | ||
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