Adhemerval Zanella b0a4eca2fc alpha: Remove s_trunc{f} implementation (BZ#22666) ... As discussed in libc-alpha [1], alpha trunc{f} implementation uses addt/suc and subt/suc and although the Alpha Architecture Handbook version 3 states that that ADDx SUBx OUTPUT Exceptions (B.3 Mapping to IEEE Standard) should not generate Inexact if INE bit is set, the Alpha 21264 [2] chip manual (A.8 IEEE Floating-Point Conformance) states that ADDx SUBx OUTPUT does generate inexact exception for inexact result regardless. As Joseph noted [3] to correctly fix it on alpha we need to either avoid the instruction or avoid any inexact bit from it being set on return from the function (while preserving the inexact bit that might be set on the entry to the function). The later will result mf_fpcr followed by a mt_fpcr to get and set the fpcr which will defeat the optimization itself. So the patch just remove the alpha optimized and rely on generic implementation. It fixes the math/test-*-{trunc} on alpha. [BZ #15479] [BZ #22666] * sysdeps/alpha/fpu/s_trunc.c: Remove file. * sysdeps/alpha/fpu/s_truncf.c: Likewise. [1] https://sourceware.org/ml/libc-alpha/2018-01/msg00114.html [2] https://www.star.bnl.gov/public/daq/HARDWARE/21264_data_sheet.pdf [3] https://sourceware.org/ml/libc-alpha/2018-01/msg00086.html Signed-off-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>		2018-01-04 17:49:17 -02:00
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aarch64
alpha	alpha: Remove s_trunc{f} implementation (BZ#22666)	2018-01-04 17:49:17 -02:00
arm	Update ARM libm-test-ulps.	2018-01-02 18:37:06 +00:00
generic
gnu
hppa
i386
ia64
ieee754
init_array
m68k
mach
microblaze
mips	Update MIPS libm-test-ulps.	2018-01-02 21:55:15 +00:00
nios2
nptl
posix
powerpc	Update powerpc-nofpu libm-test-ulps.	2018-01-02 18:38:45 +00:00
pthread
s390
sh
sparc
tile
unix	i386: In makecontext, align the stack before calling exit [BZ #22667]	2018-01-04 18:47:35 +01:00
wordsize-32
wordsize-64
x86
x86_64