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1d401d1fcc
In some cases (e.g QEMU, non-Intel/AMD CPU) the cache information can not be retrieved and the corresponding values are set to 0. Commit2d651eb926("x86: Move x86 processor cache info to cpu_features") changed the behaviour in such case by defining the __x86_shared_cache_size and __x86_data_cache_size variables to 0 instead of using the default values. This cause an issue with the i686 SSE2 optimized bzero/routine which assumes that the cache size is at least 128 bytes, and otherwise tries to zero/set the whole address space minus 128 bytes. Fix that by restoring the original code to only update __x86_shared_cache_size and __x86_data_cache_size variables if the corresponding cache sizes are not zero. Fixes bug 28784 Fixes commit2d651eb926Reviewed-by: H.J. Lu <hjl.tools@gmail.com> (cherry picked from commitc242fcce06)
91 lines
3.2 KiB
C
91 lines
3.2 KiB
C
/* x86 cache info.
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Copyright (C) 2020-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <assert.h>
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#include <unistd.h>
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#include <cpuid.h>
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#include <cpu-features.h>
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#if HAVE_TUNABLES
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# define TUNABLE_NAMESPACE cpu
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# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */
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# include <elf/dl-tunables.h>
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#endif
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#if IS_IN (libc)
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/* Data cache size for use in memory and string routines, typically
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L1 size, rounded to multiple of 256 bytes. */
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long int __x86_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
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long int __x86_data_cache_size attribute_hidden = 32 * 1024;
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/* Shared cache size for use in memory and string routines, typically
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L2 or L3 size, rounded to multiple of 256 bytes. */
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long int __x86_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
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long int __x86_shared_cache_size attribute_hidden = 1024 * 1024;
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/* Threshold to use non temporal store. */
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long int __x86_shared_non_temporal_threshold attribute_hidden;
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/* Threshold to use Enhanced REP MOVSB. */
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long int __x86_rep_movsb_threshold attribute_hidden = 2048;
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/* Threshold to use Enhanced REP STOSB. */
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long int __x86_rep_stosb_threshold attribute_hidden = 2048;
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/* Threshold to stop using Enhanced REP MOVSB. */
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long int __x86_rep_movsb_stop_threshold attribute_hidden;
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/* A bit-wise OR of string/memory requirements for optimal performance
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e.g. X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB. These bits
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are used at runtime to tune implementation behavior. */
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int __x86_string_control attribute_hidden;
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static void
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init_cacheinfo (void)
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{
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const struct cpu_features *cpu_features = __get_cpu_features ();
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long int data = cpu_features->data_cache_size;
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/* Round data cache size to multiple of 256 bytes. */
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data = data & ~255L;
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if (data > 0)
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{
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__x86_data_cache_size_half = data / 2;
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__x86_data_cache_size = data;
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}
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long int shared = cpu_features->shared_cache_size;
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/* Round shared cache size to multiple of 256 bytes. */
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shared = shared & ~255L;
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if (shared > 0)
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{
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__x86_shared_cache_size_half = shared / 2;
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__x86_shared_cache_size = shared;
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}
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__x86_shared_non_temporal_threshold
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= cpu_features->non_temporal_threshold;
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__x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold;
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__x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold;
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__x86_rep_movsb_stop_threshold = cpu_features->rep_movsb_stop_threshold;
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if (CPU_FEATURES_ARCH_P (cpu_features, Avoid_Short_Distance_REP_MOVSB))
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__x86_string_control
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|= X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB;
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}
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#endif
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