glibc/sysdeps
Joe Ramsay a15b1394b5 AArch64: Improve codegen in SVE F32 logs
Reduce MOVPRFXs by using unpredicated (non-destructive) instructions
where possible.  Similar to the recent change to AdvSIMD F32 logs,
adjust special-case arguments and bounds to allow for more optimal
register usage.  For all 3 routines one MOVPRFX remains in the
reduction, which cannot be avoided as immediate AND and ASR are both
destructive.

Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>
2024-09-23 15:44:07 +01:00
..
aarch64 AArch64: Improve codegen in SVE F32 logs 2024-09-23 15:44:07 +01:00
alpha
arc
arm
csky
generic
gnu
hppa hppa: Update libm-test-ulps 2024-09-09 09:57:42 -04:00
htl
hurd
i386 i386: Update ulps 2024-09-05 22:25:55 +02:00
ieee754
loongarch LoongArch: Fix macro redefined warning in tls-desc.S 2024-09-06 15:46:13 +08:00
m68k
mach hurd: Avoid file_check_access () RPC for access (F_OK) 2024-09-19 14:18:39 +02:00
microblaze
mips
nios2
nptl
or1k
posix
powerpc powerpc64le: Build new strtod tests with long double ABI flags (bug 32145) 2024-09-05 22:02:23 +02:00
pthread
riscv
s390
sh
sparc
unix Linux: readdir64_r should not skip d_ino == 0 entries (bug 32126) 2024-09-21 19:32:34 +02:00
wordsize-32
wordsize-64
x86
x86_64