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336 lines
9.4 KiB
ArmAsm
336 lines
9.4 KiB
ArmAsm
/* Optimized memset implementation for PowerPC.
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Copyright (C) 1997, 1999, 2000, 2003 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#include <sysdep.h>
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#include <bp-sym.h>
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#include <bp-asm.h>
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/* Define a global static that can hold the cache line size. The
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assumption is that startup code will access the "aux vector" to
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to obtain the value set by the kernel and store it into this
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variable. */
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.globl __cache_line_size
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.lcomm __cache_line_size,4,4
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/* __ptr_t [r3] memset (__ptr_t s [r3], int c [r4], size_t n [r5]));
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Returns 's'.
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The memset is done in four sizes: byte (8 bits), word (32 bits),
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32-byte blocks (256 bits) and __cache_line_size (128, 256, 1024 bits).
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There is a special case for setting whole cache lines to 0, which
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takes advantage of the dcbz instruction. */
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.section ".text"
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EALIGN (BP_SYM (memset), 5, 1)
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#define rTMP r0
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#define rRTN r3 /* initial value of 1st argument */
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#if __BOUNDED_POINTERS__
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# define rMEMP0 r4 /* original value of 1st arg */
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# define rCHR r5 /* char to set in each byte */
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# define rLEN r6 /* length of region to set */
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# define rMEMP r10 /* address at which we are storing */
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#else
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# define rMEMP0 r3 /* original value of 1st arg */
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# define rCHR r4 /* char to set in each byte */
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# define rLEN r5 /* length of region to set */
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# define rMEMP r6 /* address at which we are storing */
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#endif
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#define rALIGN r7 /* number of bytes we are setting now (when aligning) */
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#define rMEMP2 r8
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#define rPOS32 r7 /* constant +32 for clearing with dcbz */
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#define rNEG64 r8 /* constant -64 for clearing with dcbz */
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#define rNEG32 r9 /* constant -32 for clearing with dcbz */
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#define rGOT r9 /* Address of the Global Offset Table. */
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#define rCLS r8 /* Cache line size obtained from static. */
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#define rCLM r9 /* Cache line size mask to check for cache alignment. */
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#if __BOUNDED_POINTERS__
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cmplwi cr1, rRTN, 0
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CHECK_BOUNDS_BOTH_WIDE (rMEMP0, rTMP, rTMP2, rLEN)
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beq cr1, L(b0)
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STORE_RETURN_VALUE (rMEMP0)
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STORE_RETURN_BOUNDS (rTMP, rTMP2)
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L(b0):
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#endif
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/* take care of case for size <= 4 */
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cmplwi cr1, rLEN, 4
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andi. rALIGN, rMEMP0, 3
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mr rMEMP, rMEMP0
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ble- cr1, L(small)
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/* align to word boundary */
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cmplwi cr5, rLEN, 31
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rlwimi rCHR, rCHR, 8, 16, 23
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beq+ L(aligned) /* 8th instruction from .align */
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mtcrf 0x01, rMEMP0
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subfic rALIGN, rALIGN, 4
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add rMEMP, rMEMP, rALIGN
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sub rLEN, rLEN, rALIGN
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bf+ 31, L(g0)
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stb rCHR, 0(rMEMP0)
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bt 30, L(aligned)
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L(g0): sth rCHR, -2(rMEMP) /* 16th instruction from .align */
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/* take care of case for size < 31 */
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L(aligned):
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mtcrf 0x01, rLEN
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rlwimi rCHR, rCHR, 16, 0, 15
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ble cr5, L(medium)
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/* align to cache line boundary... */
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andi. rALIGN, rMEMP, 0x1C
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subfic rALIGN, rALIGN, 0x20
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beq L(caligned)
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mtcrf 0x01, rALIGN
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add rMEMP, rMEMP, rALIGN
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sub rLEN, rLEN, rALIGN
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cmplwi cr1, rALIGN, 0x10
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mr rMEMP2, rMEMP
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bf 28, L(a1)
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stw rCHR, -4(rMEMP2)
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stwu rCHR, -8(rMEMP2)
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L(a1): blt cr1, L(a2)
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stw rCHR, -4(rMEMP2) /* 32nd instruction from .align */
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stw rCHR, -8(rMEMP2)
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stw rCHR, -12(rMEMP2)
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stwu rCHR, -16(rMEMP2)
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L(a2): bf 29, L(caligned)
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stw rCHR, -4(rMEMP2)
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/* now aligned to a cache line. */
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L(caligned):
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cmplwi cr1, rCHR, 0
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clrrwi. rALIGN, rLEN, 5
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mtcrf 0x01, rLEN /* 40th instruction from .align */
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/* Check if we can use the special case for clearing memory using dcbz.
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This requires that we know the correct cache line size for this
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processor. Getting the __cache_line_size may require establishing GOT
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addressability, so branch out of line to set this up. */
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beq cr1, L(checklinesize)
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/* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.
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Can't assume that rCHR is zero or that the cache line size is either
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32-bytes or even known. */
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L(nondcbz):
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srwi rTMP, rALIGN, 5
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mtctr rTMP
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beq L(medium) /* we may not actually get to do a full line */
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clrlwi. rLEN, rLEN, 27
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add rMEMP, rMEMP, rALIGN
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li rNEG64, -0x40
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bdz L(cloopdone) /* 48th instruction from .align */
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/* We can't use dcbz here as we don't know the cache line size. We can
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use "data cache block touch for store", which is safe. */
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L(c3): dcbtst rNEG64, rMEMP
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stw rCHR, -4(rMEMP)
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stw rCHR, -8(rMEMP)
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stw rCHR, -12(rMEMP)
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stw rCHR, -16(rMEMP)
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nop /* let 601 fetch last 4 instructions of loop */
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stw rCHR, -20(rMEMP)
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stw rCHR, -24(rMEMP) /* 56th instruction from .align */
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nop /* let 601 fetch first 8 instructions of loop */
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stw rCHR, -28(rMEMP)
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stwu rCHR, -32(rMEMP)
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bdnz L(c3)
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L(cloopdone):
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stw rCHR, -4(rMEMP)
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stw rCHR, -8(rMEMP)
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stw rCHR, -12(rMEMP)
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stw rCHR, -16(rMEMP) /* 64th instruction from .align */
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stw rCHR, -20(rMEMP)
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cmplwi cr1, rLEN, 16
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stw rCHR, -24(rMEMP)
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stw rCHR, -28(rMEMP)
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stwu rCHR, -32(rMEMP)
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beqlr
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add rMEMP, rMEMP, rALIGN
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b L(medium_tail2) /* 72nd instruction from .align */
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.align 5
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nop
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/* Clear cache lines of memory in 128-byte chunks.
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This code is optimized for processors with 32-byte cache lines.
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It is further optimized for the 601 processor, which requires
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some care in how the code is aligned in the i-cache. */
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L(zloopstart):
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clrlwi rLEN, rLEN, 27
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mtcrf 0x02, rALIGN
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srwi. rTMP, rALIGN, 7
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mtctr rTMP
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li rPOS32, 0x20
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li rNEG64, -0x40
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cmplwi cr1, rLEN, 16 /* 8 */
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bf 26, L(z0)
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dcbz 0, rMEMP
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addi rMEMP, rMEMP, 0x20
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L(z0): li rNEG32, -0x20
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bf 25, L(z1)
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dcbz 0, rMEMP
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dcbz rPOS32, rMEMP
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addi rMEMP, rMEMP, 0x40 /* 16 */
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L(z1): cmplwi cr5, rLEN, 0
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beq L(medium)
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L(zloop):
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dcbz 0, rMEMP
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dcbz rPOS32, rMEMP
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addi rMEMP, rMEMP, 0x80
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dcbz rNEG64, rMEMP
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dcbz rNEG32, rMEMP
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bdnz L(zloop)
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beqlr cr5
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b L(medium_tail2)
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.align 5
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L(small):
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/* Memset of 4 bytes or less. */
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cmplwi cr5, rLEN, 1
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cmplwi cr1, rLEN, 3
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bltlr cr5
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stb rCHR, 0(rMEMP)
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beqlr cr5
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nop
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stb rCHR, 1(rMEMP)
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bltlr cr1
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stb rCHR, 2(rMEMP)
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beqlr cr1
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nop
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stb rCHR, 3(rMEMP)
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blr
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/* Memset of 0-31 bytes. */
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.align 5
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L(medium):
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cmplwi cr1, rLEN, 16
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L(medium_tail2):
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add rMEMP, rMEMP, rLEN
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L(medium_tail):
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bt- 31, L(medium_31t)
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bt- 30, L(medium_30t)
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L(medium_30f):
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bt- 29, L(medium_29t)
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L(medium_29f):
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bge- cr1, L(medium_27t)
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bflr- 28
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stw rCHR, -4(rMEMP) /* 8th instruction from .align */
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stw rCHR, -8(rMEMP)
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blr
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L(medium_31t):
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stbu rCHR, -1(rMEMP)
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bf- 30, L(medium_30f)
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L(medium_30t):
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sthu rCHR, -2(rMEMP)
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bf- 29, L(medium_29f)
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L(medium_29t):
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stwu rCHR, -4(rMEMP)
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blt- cr1, L(medium_27f) /* 16th instruction from .align */
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L(medium_27t):
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stw rCHR, -4(rMEMP)
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stw rCHR, -8(rMEMP)
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stw rCHR, -12(rMEMP)
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stwu rCHR, -16(rMEMP)
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L(medium_27f):
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bflr- 28
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L(medium_28t):
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stw rCHR, -4(rMEMP)
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stw rCHR, -8(rMEMP)
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blr
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L(checklinesize):
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#ifdef SHARED
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mflr rTMP
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/* If the remaining length is less the 32 bytes then don't bother getting
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the cache line size. */
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beq L(medium)
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/* Establishes GOT addressability so we can load __cache_line_size
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from static. This value was set from the aux vector during startup. */
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bl _GLOBAL_OFFSET_TABLE_@local-4
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mflr rGOT
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lwz rGOT,__cache_line_size@got(rGOT)
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lwz rCLS,0(rGOT)
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mtlr rTMP
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#else
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/* Load __cache_line_size from static. This value was set from the
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aux vector during startup. */
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lis rCLS,__cache_line_size@ha
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/* If the remaining length is less the 32 bytes then don't bother getting
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the cache line size. */
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beq L(medium)
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lwz rCLS,__cache_line_size@l(rCLS)
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#endif
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/*If the cache line size was not set then goto to L(nondcbz), which is
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safe for any cache line size. */
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cmplwi cr1,rCLS,0
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beq cr1,L(nondcbz)
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/* If the cache line size is 32 bytes then goto to L(zloopstart),
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which is coded specificly for 32-byte lines (and 601). */
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cmplwi cr1,rCLS,32
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beq cr1,L(zloopstart)
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/* Now we know the cache line size and it is not 32-bytes. However
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we may not yet be aligned to the cache line and may have a partial
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line to fill. Touch it 1st to fetch the cache line. */
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dcbtst 0,rMEMP
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addi rCLM,rCLS,-1
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L(getCacheAligned):
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cmplwi cr1,rLEN,32
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and. rTMP,rCLM,rMEMP
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blt cr1,L(handletail32)
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beq L(cacheAligned)
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/* We are not aligned to start of a cache line yet. Store 32-byte
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of data and test again. */
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addi rMEMP,rMEMP,32
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addi rLEN,rLEN,-32
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stw rCHR,-32(rMEMP)
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stw rCHR,-28(rMEMP)
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stw rCHR,-24(rMEMP)
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stw rCHR,-20(rMEMP)
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stw rCHR,-16(rMEMP)
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stw rCHR,-12(rMEMP)
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stw rCHR,-8(rMEMP)
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stw rCHR,-4(rMEMP)
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b L(getCacheAligned)
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/* Now we are aligned to the cache line and can use dcbz. */
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L(cacheAligned):
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cmplw cr1,rLEN,rCLS
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blt cr1,L(handletail32)
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dcbz 0,rMEMP
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subf rLEN,rCLS,rLEN
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add rMEMP,rMEMP,rCLS
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b L(cacheAligned)
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/* We are here because; the cache line size was set, it was not
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32-bytes, and the remainder (rLEN) is now less than the actual cache
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line size. Set up the preconditions for L(nondcbz) and go there to
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store the remaining bytes. */
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L(handletail32):
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clrrwi. rALIGN, rLEN, 5
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b L(nondcbz)
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END (BP_SYM (memset))
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libc_hidden_builtin_def (memset)
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