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git://sourceware.org/git/glibc.git
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81cb7a0b2b
This semi-mechanical patch removes all uses and definitions of the
sfi_breg, sfi_pld, and sfi_sp macros from various ARM-specific
assembly files. These were only used by NaCl.
* sysdeps/arm/sysdep.h
(ARM_SFI_MACROS, sfi_breg, sfi_pld, sfi_sp): Delete definitions.
* sysdeps/arm/__longjmp.S, sysdeps/arm/add_n.S
* sysdeps/arm/addmul_1.S, sysdeps/arm/arm-mcount.S
* sysdeps/arm/armv6/rawmemchr.S, sysdeps/arm/armv6/strchr.S
* sysdeps/arm/armv6/strcpy.S, sysdeps/arm/armv6/strlen.S
* sysdeps/arm/armv6/strrchr.S, sysdeps/arm/armv6t2/memchr.S
* sysdeps/arm/armv6t2/strlen.S
* sysdeps/arm/armv7/multiarch/memcpy_impl.S
* sysdeps/arm/armv7/strcmp.S, sysdeps/arm/dl-tlsdesc.S
* sysdeps/arm/memcpy.S, sysdeps/arm/memmove.S
* sysdeps/arm/memset.S, sysdeps/arm/setjmp.S
* sysdeps/arm/strlen.S, sysdeps/arm/submul_1.S:
Remove all uses of sfi_breg, sfi_pld, and sfi_sp.
91 lines
2.3 KiB
ArmAsm
91 lines
2.3 KiB
ArmAsm
/* mpn_add_n -- add (or subtract) bignums.
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Copyright (C) 2013-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include <arm-features.h>
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.syntax unified
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.text
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#ifdef USE_AS_SUB_N
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# define INITC cmp r0, r0
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# define OPC sbcs
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# define RETC sbc r0, r0, r0; neg r0, r0
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# define FUNC __mpn_sub_n
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#else
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# define INITC cmn r0, #0
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# define OPC adcs
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# define RETC mov r0, #0; adc r0, r0, r0
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# define FUNC __mpn_add_n
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#endif
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/* mp_limb_t mpn_add_n(res_ptr, src1_ptr, src2_ptr, size) */
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ENTRY (FUNC)
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push { r4, r5, r6, r7, r8, r10, lr }
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cfi_adjust_cfa_offset (28)
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cfi_rel_offset (r4, 0)
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cfi_rel_offset (r5, 4)
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cfi_rel_offset (r6, 8)
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cfi_rel_offset (r7, 12)
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cfi_rel_offset (r8, 16)
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cfi_rel_offset (r10, 20)
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cfi_rel_offset (lr, 24)
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INITC /* initialize carry flag */
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tst r3, #1 /* count & 1 == 1? */
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add lr, r1, r3, lsl #2 /* compute end src1 */
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beq 1f
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ldr r4, [r1], #4 /* do one to make count even */
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ldr r5, [r2], #4
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OPC r4, r4, r5
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teq r1, lr /* end of count? (preserve carry) */
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str r4, [r0], #4
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beq 9f
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1:
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tst r3, #2 /* count & 2 == 2? */
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beq 2f
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ldm r1!, { r4, r5 } /* do two to make count 0 mod 4 */
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ldm r2!, { r6, r7 }
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OPC r4, r4, r6
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OPC r5, r5, r7
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teq r1, lr /* end of count? */
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stm r0!, { r4, r5 }
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beq 9f
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2:
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ldm r1!, { r3, r5, r7, r10 } /* do four each loop */
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ldm r2!, { r4, r6, r8, ip }
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OPC r3, r3, r4
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OPC r5, r5, r6
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OPC r7, r7, r8
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OPC r10, r10, ip
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teq r1, lr
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stm r0!, { r3, r5, r7, r10 }
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bne 2b
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9:
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RETC /* copy carry out */
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#ifndef ARM_ALWAYS_BX
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pop { r4, r5, r6, r7, r8, r10, pc }
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#else
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pop { r4, r5, r6, r7, r8, r10, lr }
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bx lr
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#endif
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END (FUNC)
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