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f53ffc9b90
commit 2d651eb926
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri Sep 18 07:55:14 2020 -0700
x86: Move x86 processor cache info to cpu_features
missed _SC_LEVEL1_ICACHE_LINESIZE.
1. Add level1_icache_linesize to struct cpu_features.
2. Initialize level1_icache_linesize by calling handle_intel,
handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE.
3. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE.
Reviewed-by: Carlos O'Donell <carlos@redhat.com>
89 lines
2.6 KiB
C
89 lines
2.6 KiB
C
/* x86 cache info.
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Copyright (C) 2003-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#if IS_IN (libc)
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#include <unistd.h>
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#include <ldsodefs.h>
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/* Get the value of the system variable NAME. */
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long int
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attribute_hidden
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__cache_sysconf (int name)
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{
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const struct cpu_features *cpu_features = __get_cpu_features ();
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switch (name)
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{
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case _SC_LEVEL1_ICACHE_SIZE:
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return cpu_features->level1_icache_size;
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case _SC_LEVEL1_ICACHE_LINESIZE:
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return cpu_features->level1_icache_linesize;
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case _SC_LEVEL1_DCACHE_SIZE:
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return cpu_features->level1_dcache_size;
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case _SC_LEVEL1_DCACHE_ASSOC:
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return cpu_features->level1_dcache_assoc;
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case _SC_LEVEL1_DCACHE_LINESIZE:
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return cpu_features->level1_dcache_linesize;
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case _SC_LEVEL2_CACHE_SIZE:
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return cpu_features->level2_cache_size;
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case _SC_LEVEL2_CACHE_ASSOC:
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return cpu_features->level2_cache_assoc;
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case _SC_LEVEL2_CACHE_LINESIZE:
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return cpu_features->level2_cache_linesize;
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case _SC_LEVEL3_CACHE_SIZE:
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return cpu_features->level3_cache_size;
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case _SC_LEVEL3_CACHE_ASSOC:
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return cpu_features->level3_cache_assoc;
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case _SC_LEVEL3_CACHE_LINESIZE:
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return cpu_features->level3_cache_linesize;
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case _SC_LEVEL4_CACHE_SIZE:
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return cpu_features->level4_cache_size;
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default:
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break;
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}
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return -1;
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}
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# ifdef SHARED
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/* NB: In libc.a, cacheinfo.h is included in libc-start.c. In libc.so,
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cacheinfo.h is included here and call init_cacheinfo by initializing
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a dummy function pointer via IFUNC relocation after CPU features in
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ld.so have been initialized by DL_PLATFORM_INIT or IFUNC relocation. */
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# include <cacheinfo.h>
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# include <ifunc-init.h>
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extern void __x86_cacheinfo (void) attribute_hidden;
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void (*const __x86_cacheinfo_p) (void) attribute_hidden
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= __x86_cacheinfo;
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__ifunc (__x86_cacheinfo, __x86_cacheinfo, NULL, void, init_cacheinfo);
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# endif
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#endif
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