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9f78a7c1d0
When glibc is built with ISA level 3 or higher by default, the resulting glibc binaries won't run on SSE or FMA4 processors. Exclude SSE, AVX and FMA4 variants in libm multiarch when ISA level 3 or higher is enabled by default. When glibc is built with ISA level 2 enabled by default, only keep SSE4.1 variant. Fixes BZ 31335. NB: elf/tst-valgrind-smoke test fails with ISA level 4, because valgrind doesn't support AVX512 instructions: https://bugs.kde.org/show_bug.cgi?id=383010 Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
114 lines
3.2 KiB
Plaintext
114 lines
3.2 KiB
Plaintext
GLIBC_PROVIDES dnl See aclocal.m4 in the top level source directory.
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# Local configure fragment for sysdeps/x86.
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# Check if linker supports x86 ISA level.
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AC_CACHE_CHECK([for linker x86 ISA level support],
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libc_cv_include_x86_isa_level, [dnl
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cat > conftest1.S <<EOF
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#ifdef __LP64__
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# define P2ALIGN 3
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#else
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# define P2ALIGN 2
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#endif
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.section ".note.gnu.property", "a"
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.p2align P2ALIGN
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.long 1f - 0f /* name length. */
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.long 4f - 1f /* data length. */
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/* NT_GNU_PROPERTY_TYPE_0 */
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.long 5 /* note type. */
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0:
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.asciz "GNU" /* vendor name. */
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1:
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.p2align P2ALIGN
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/* GNU_PROPERTY_X86_ISA_1_NEEDED */
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.long 0xc0008002 /* pr_type. */
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.long 3f - 2f /* pr_datasz. */
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2:
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.long 0x1
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3:
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.p2align P2ALIGN
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4:
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EOF
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cat > conftest2.S <<EOF
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#ifdef __LP64__
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# define P2ALIGN 3
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#else
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# define P2ALIGN 2
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#endif
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.section ".note.gnu.property", "a"
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.p2align P2ALIGN
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.long 1f - 0f /* name length. */
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.long 4f - 1f /* data length. */
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/* NT_GNU_PROPERTY_TYPE_0 */
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.long 5 /* note type. */
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0:
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.asciz "GNU" /* vendor name. */
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1:
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.p2align P2ALIGN
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/* GNU_PROPERTY_X86_ISA_1_NEEDED */
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.long 0xc0008002 /* pr_type. */
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.long 3f - 2f /* pr_datasz. */
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2:
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.long 0x2
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3:
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.p2align P2ALIGN
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4:
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EOF
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libc_cv_include_x86_isa_level=no
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if AC_TRY_COMMAND(${CC-cc} $CFLAGS $CPPFLAGS -nostartfiles -nostdlib -r -o conftest conftest1.S conftest2.S); then
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count=`LC_ALL=C $READELF -n conftest | grep NT_GNU_PROPERTY_TYPE_0 | wc -l`
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if test "$count" = 1; then
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libc_cv_include_x86_isa_level=yes
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fi
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fi
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rm -f conftest*])
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if test $libc_cv_include_x86_isa_level = yes; then
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AC_DEFINE(INCLUDE_X86_ISA_LEVEL)
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AC_CACHE_CHECK([for LAHF/SAHF instruction support],
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libc_cv_have_x86_lahf_sahf, [dnl
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libc_cv_have_x86_lahf_sahf=no
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if AC_TRY_COMMAND(${CC-cc} $CFLAGS $CPPFLAGS -fverbose-asm -S -o - -x c /dev/null) | grep -qE '(-msahf\b|-march=x86-64-v)'; then
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libc_cv_have_x86_lahf_sahf=yes
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fi])
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if test $libc_cv_have_x86_lahf_sahf = yes; then
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AC_DEFINE(HAVE_X86_LAHF_SAHF)
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ISAFLAG="-DHAVE_X86_LAHF_SAHF"
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fi
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AC_CACHE_CHECK([for MOVBE instruction support],
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libc_cv_have_x86_movbe, [dnl
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libc_cv_have_x86_movbe=no
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if AC_TRY_COMMAND(${CC-cc} $CFLAGS $CPPFLAGS -fverbose-asm -S -o - -x c /dev/null) | grep -qE '(-mmovbe\b|-march=x86-64-v(@<:@3-9@:>@|@<:@1-9@:>@@<:@0-9@:>@))'; then
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libc_cv_have_x86_movbe=yes
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fi])
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if test $libc_cv_have_x86_movbe = yes; then
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AC_DEFINE(HAVE_X86_MOVBE)
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ISAFLAG="$ISAFLAG -DHAVE_X86_MOVBE"
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fi
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# Check for ISA level support.
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AC_CACHE_CHECK([for ISA level support],
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libc_cv_have_x86_isa_level, [dnl
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cat > conftest.c <<EOF
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#include <sysdeps/x86/isa-level.h>
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#if MINIMUM_X86_ISA_LEVEL >= 4
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libc_cv_have_x86_isa_level=4
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#elif MINIMUM_X86_ISA_LEVEL == 3
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libc_cv_have_x86_isa_level=3
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#elif MINIMUM_X86_ISA_LEVEL == 2
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libc_cv_have_x86_isa_level=2
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#else
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libc_cv_have_x86_isa_level=baseline
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#endif
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EOF
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eval `${CC-cc} $CFLAGS $CPPFLAGS $ISAFLAG -I$srcdir -E conftest.c | grep libc_cv_have_x86_isa_level`
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rm -rf conftest*])
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else
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libc_cv_have_x86_isa_level=baseline
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fi
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LIBC_CONFIG_VAR([have-x86-isa-level], [$libc_cv_have_x86_isa_level])
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LIBC_CONFIG_VAR([x86-isa-level-3-or-above], [3 4])
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LIBC_CONFIG_VAR([enable-x86-isa-level], [$libc_cv_include_x86_isa_level])
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dnl Static PIE is supported.
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AC_DEFINE(SUPPORT_STATIC_PIE)
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