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2ff16e041a
variable. Remove superfluous memory clobber. * include/atomic.h: Syntax braino fix. * posix/tst-nice.c (do_test): Use %m formats instead of printing errno in decimal. Don't bail if niced at start. Just check that nice call bumps the total at all.
167 lines
5.0 KiB
C
167 lines
5.0 KiB
C
/* Atomic operations. PowerPC version.
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Copyright (C) 2003 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#include <stdint.h>
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typedef int8_t atomic8_t;
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typedef uint8_t uatomic8_t;
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typedef int_fast8_t atomic_fast8_t;
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typedef uint_fast8_t uatomic_fast8_t;
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typedef int16_t atomic16_t;
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typedef uint16_t uatomic16_t;
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typedef int_fast16_t atomic_fast16_t;
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typedef uint_fast16_t uatomic_fast16_t;
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef int64_t atomic64_t;
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typedef uint64_t uatomic64_t;
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typedef int_fast64_t atomic_fast64_t;
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typedef uint_fast64_t uatomic_fast64_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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#define __arch_compare_and_exchange_8_acq(mem, newval, oldval) \
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(abort (), 0)
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#define __arch_compare_and_exchange_16_acq(mem, newval, oldval) \
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(abort (), 0)
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#ifdef UP
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# define __ARCH_ACQ_INSTR ""
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# define __ARCH_REL_INSTR ""
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#else
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# define __ARCH_ACQ_INSTR "isync"
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# define __ARCH_REL_INSTR "sync"
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#endif
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/*
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* XXX At present these have both acquire and release semantics.
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* Ultimately we should do separate _acq and _rel versions.
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*/
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/*
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* XXX this may not work properly on 64-bit if the register
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* containing oldval has the high half non-zero for some reason.
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*/
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#define __arch_compare_and_exchange_32_acq(mem, newval, oldval) \
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({ \
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unsigned int __tmp; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: lwarx %0,0,%1\n" \
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" subf. %0,%2,%0\n" \
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" bne 2f\n" \
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" stwcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "r" (mem), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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#ifdef __powerpc64__
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# define __arch_compare_and_exchange_64_acq(mem, newval, oldval)\
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({ \
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unsigned long __tmp; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%1\n" \
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" subf. %0,%2,%0\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "r" (mem), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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#else /* powerpc32 */
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# define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
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(abort (), 0)
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#endif
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#define atomic_exchange(mem, value) \
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({ if (sizeof (*mem) != 4) \
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abort (); \
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int __val; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: lwarx %0,0,%2\n" \
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" stwcx. %3,0,%2\n" \
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" bne- 1b" \
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: "=&r" (__val), "=m" (*mem) \
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: "r" (mem), "r" (value), "1" (*mem) \
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: "cr0"); \
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__val; })
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#define atomic_exchange_and_add(mem, value) \
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({ if (sizeof (*mem) != 4) \
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abort (); \
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int __val, __tmp; \
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__asm __volatile ("1: lwarx %0,0,%3\n" \
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" addi %1,%0,%4\n" \
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" stwcx. %1,0,%3\n" \
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" bne- 1b" \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "r" (mem), "I" (value), "2" (*mem) \
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: "cr0"); \
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__val; \
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})
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/* Decrement *MEM if it is > 0, and return the old value. */
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#define atomic_decrement_if_positive(mem) \
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({ if (sizeof (*mem) != 4) \
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abort (); \
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int __val, __tmp; \
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__asm __volatile ("1: lwarx %0,0,%3\n" \
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" cmpwi 0,%0,0\n" \
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" addi %1,%0,-1\n" \
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" ble 2f\n" \
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" stwcx. %1,0,%3\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "r" (mem), "2" (*mem) \
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: "cr0"); \
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__val; \
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})
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#define atomic_full_barrier() __asm ("sync" ::: "memory")
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#ifdef __powerpc64__
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# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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#else
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# define atomic_read_barrier() __asm ("sync" ::: "memory")
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#endif
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#define atomic_write_barrier() __asm ("eieio" ::: "memory")
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