mirror of
git://sourceware.org/git/glibc.git
synced 2024-11-21 01:12:26 +08:00
5a82c74822
Also, change sources.redhat.com to sourceware.org.
This patch was automatically generated by running the following shell
script, which uses GNU sed, and which avoids modifying files imported
from upstream:
sed -ri '
s,(http|ftp)(://(.*\.)?(gnu|fsf|sourceware)\.org($|[^.]|\.[^a-z])),https\2,g
s,(http|ftp)(://(.*\.)?)sources\.redhat\.com($|[^.]|\.[^a-z]),https\2sourceware.org\4,g
' \
$(find $(git ls-files) -prune -type f \
! -name '*.po' \
! -name 'ChangeLog*' \
! -path COPYING ! -path COPYING.LIB \
! -path manual/fdl-1.3.texi ! -path manual/lgpl-2.1.texi \
! -path manual/texinfo.tex ! -path scripts/config.guess \
! -path scripts/config.sub ! -path scripts/install-sh \
! -path scripts/mkinstalldirs ! -path scripts/move-if-change \
! -path INSTALL ! -path locale/programs/charmap-kw.h \
! -path po/libc.pot ! -path sysdeps/gnu/errlist.c \
! '(' -name configure \
-execdir test -f configure.ac -o -f configure.in ';' ')' \
! '(' -name preconfigure \
-execdir test -f preconfigure.ac ';' ')' \
-print)
and then by running 'make dist-prepare' to regenerate files built
from the altered files, and then executing the following to cleanup:
chmod a+x sysdeps/unix/sysv/linux/riscv/configure
# Omit irrelevant whitespace and comment-only changes,
# perhaps from a slightly-different Autoconf version.
git checkout -f \
sysdeps/csky/configure \
sysdeps/hppa/configure \
sysdeps/riscv/configure \
sysdeps/unix/sysv/linux/csky/configure
# Omit changes that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/powerpc/powerpc64/ppc-mcount.S: trailing lines
git checkout -f \
sysdeps/powerpc/powerpc64/ppc-mcount.S \
sysdeps/unix/sysv/linux/s390/s390-64/syscall.S
# Omit change that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S: last line does not end in newline
git checkout -f sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S
574 lines
16 KiB
ArmAsm
574 lines
16 KiB
ArmAsm
/* memmove/memcpy/mempcpy with unaligned load/store and rep movsb
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Copyright (C) 2016-2019 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* memmove/memcpy/mempcpy is implemented as:
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1. Use overlapping load and store to avoid branch.
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2. Load all sources into registers and store them together to avoid
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possible address overlap between source and destination.
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3. If size is 8 * VEC_SIZE or less, load all sources into registers
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and store them together.
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4. If address of destination > address of source, backward copy
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4 * VEC_SIZE at a time with unaligned load and aligned store.
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Load the first 4 * VEC and last VEC before the loop and store
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them after the loop to support overlapping addresses.
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5. Otherwise, forward copy 4 * VEC_SIZE at a time with unaligned
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load and aligned store. Load the last 4 * VEC and first VEC
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before the loop and store them after the loop to support
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overlapping addresses.
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6. If size >= __x86_shared_non_temporal_threshold and there is no
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overlap between destination and source, use non-temporal store
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instead of aligned store. */
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#include <sysdep.h>
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#ifndef MEMCPY_SYMBOL
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# define MEMCPY_SYMBOL(p,s) MEMMOVE_SYMBOL(p, s)
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#endif
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#ifndef MEMPCPY_SYMBOL
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# define MEMPCPY_SYMBOL(p,s) MEMMOVE_SYMBOL(p, s)
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#endif
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#ifndef MEMMOVE_CHK_SYMBOL
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# define MEMMOVE_CHK_SYMBOL(p,s) MEMMOVE_SYMBOL(p, s)
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#endif
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#ifndef VZEROUPPER
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# if VEC_SIZE > 16
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# define VZEROUPPER vzeroupper
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# else
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# define VZEROUPPER
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# endif
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#endif
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/* Threshold to use Enhanced REP MOVSB. Since there is overhead to set
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up REP MOVSB operation, REP MOVSB isn't faster on short data. The
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memcpy micro benchmark in glibc shows that 2KB is the approximate
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value above which REP MOVSB becomes faster than SSE2 optimization
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on processors with Enhanced REP MOVSB. Since larger register size
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can move more data with a single load and store, the threshold is
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higher with larger register size. */
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#ifndef REP_MOVSB_THRESHOLD
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# define REP_MOVSB_THRESHOLD (2048 * (VEC_SIZE / 16))
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#endif
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#ifndef PREFETCH
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# define PREFETCH(addr) prefetcht0 addr
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#endif
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/* Assume 64-byte prefetch size. */
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#ifndef PREFETCH_SIZE
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# define PREFETCH_SIZE 64
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#endif
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#define PREFETCHED_LOAD_SIZE (VEC_SIZE * 4)
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#if PREFETCH_SIZE == 64
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# if PREFETCHED_LOAD_SIZE == PREFETCH_SIZE
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# define PREFETCH_ONE_SET(dir, base, offset) \
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PREFETCH ((offset)base)
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# elif PREFETCHED_LOAD_SIZE == 2 * PREFETCH_SIZE
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# define PREFETCH_ONE_SET(dir, base, offset) \
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PREFETCH ((offset)base); \
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PREFETCH ((offset + dir * PREFETCH_SIZE)base)
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# elif PREFETCHED_LOAD_SIZE == 4 * PREFETCH_SIZE
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# define PREFETCH_ONE_SET(dir, base, offset) \
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PREFETCH ((offset)base); \
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PREFETCH ((offset + dir * PREFETCH_SIZE)base); \
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PREFETCH ((offset + dir * PREFETCH_SIZE * 2)base); \
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PREFETCH ((offset + dir * PREFETCH_SIZE * 3)base)
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# else
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# error Unsupported PREFETCHED_LOAD_SIZE!
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# endif
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#else
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# error Unsupported PREFETCH_SIZE!
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#endif
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#ifndef SECTION
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# error SECTION is not defined!
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#endif
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.section SECTION(.text),"ax",@progbits
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#if defined SHARED && IS_IN (libc)
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ENTRY (MEMMOVE_CHK_SYMBOL (__mempcpy_chk, unaligned))
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END (MEMMOVE_CHK_SYMBOL (__mempcpy_chk, unaligned))
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#endif
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ENTRY (MEMPCPY_SYMBOL (__mempcpy, unaligned))
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mov %RDI_LP, %RAX_LP
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add %RDX_LP, %RAX_LP
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jmp L(start)
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END (MEMPCPY_SYMBOL (__mempcpy, unaligned))
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#if defined SHARED && IS_IN (libc)
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ENTRY (MEMMOVE_CHK_SYMBOL (__memmove_chk, unaligned))
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END (MEMMOVE_CHK_SYMBOL (__memmove_chk, unaligned))
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#endif
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ENTRY (MEMMOVE_SYMBOL (__memmove, unaligned))
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movq %rdi, %rax
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L(start):
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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cmp $VEC_SIZE, %RDX_LP
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jb L(less_vec)
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cmp $(VEC_SIZE * 2), %RDX_LP
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ja L(more_2x_vec)
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#if !defined USE_MULTIARCH || !IS_IN (libc)
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L(last_2x_vec):
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#endif
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/* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */
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VMOVU (%rsi), %VEC(0)
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VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(1)
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VMOVU %VEC(0), (%rdi)
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VMOVU %VEC(1), -VEC_SIZE(%rdi,%rdx)
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VZEROUPPER
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#if !defined USE_MULTIARCH || !IS_IN (libc)
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L(nop):
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#endif
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ret
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#if defined USE_MULTIARCH && IS_IN (libc)
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END (MEMMOVE_SYMBOL (__memmove, unaligned))
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# if VEC_SIZE == 16
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ENTRY (__mempcpy_chk_erms)
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END (__mempcpy_chk_erms)
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/* Only used to measure performance of REP MOVSB. */
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ENTRY (__mempcpy_erms)
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mov %RDI_LP, %RAX_LP
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/* Skip zero length. */
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test %RDX_LP, %RDX_LP
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jz 2f
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add %RDX_LP, %RAX_LP
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jmp L(start_movsb)
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END (__mempcpy_erms)
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ENTRY (__memmove_chk_erms)
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END (__memmove_chk_erms)
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ENTRY (__memmove_erms)
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movq %rdi, %rax
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/* Skip zero length. */
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test %RDX_LP, %RDX_LP
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jz 2f
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L(start_movsb):
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mov %RDX_LP, %RCX_LP
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cmp %RSI_LP, %RDI_LP
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jb 1f
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/* Source == destination is less common. */
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je 2f
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lea (%rsi,%rcx), %RDX_LP
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cmp %RDX_LP, %RDI_LP
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jb L(movsb_backward)
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1:
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rep movsb
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2:
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ret
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L(movsb_backward):
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leaq -1(%rdi,%rcx), %rdi
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leaq -1(%rsi,%rcx), %rsi
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std
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rep movsb
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cld
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ret
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END (__memmove_erms)
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strong_alias (__memmove_erms, __memcpy_erms)
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strong_alias (__memmove_chk_erms, __memcpy_chk_erms)
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# endif
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# ifdef SHARED
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ENTRY (MEMMOVE_CHK_SYMBOL (__mempcpy_chk, unaligned_erms))
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END (MEMMOVE_CHK_SYMBOL (__mempcpy_chk, unaligned_erms))
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# endif
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ENTRY (MEMMOVE_SYMBOL (__mempcpy, unaligned_erms))
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mov %RDI_LP, %RAX_LP
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add %RDX_LP, %RAX_LP
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jmp L(start_erms)
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END (MEMMOVE_SYMBOL (__mempcpy, unaligned_erms))
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# ifdef SHARED
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ENTRY (MEMMOVE_CHK_SYMBOL (__memmove_chk, unaligned_erms))
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END (MEMMOVE_CHK_SYMBOL (__memmove_chk, unaligned_erms))
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# endif
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ENTRY (MEMMOVE_SYMBOL (__memmove, unaligned_erms))
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movq %rdi, %rax
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L(start_erms):
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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cmp $VEC_SIZE, %RDX_LP
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jb L(less_vec)
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cmp $(VEC_SIZE * 2), %RDX_LP
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ja L(movsb_more_2x_vec)
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L(last_2x_vec):
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/* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */
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VMOVU (%rsi), %VEC(0)
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VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(1)
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VMOVU %VEC(0), (%rdi)
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VMOVU %VEC(1), -VEC_SIZE(%rdi,%rdx)
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L(return):
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VZEROUPPER
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ret
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L(movsb):
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cmpq __x86_shared_non_temporal_threshold(%rip), %rdx
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jae L(more_8x_vec)
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cmpq %rsi, %rdi
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jb 1f
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/* Source == destination is less common. */
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je L(nop)
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leaq (%rsi,%rdx), %r9
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cmpq %r9, %rdi
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/* Avoid slow backward REP MOVSB. */
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# if REP_MOVSB_THRESHOLD <= (VEC_SIZE * 8)
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# error Unsupported REP_MOVSB_THRESHOLD and VEC_SIZE!
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# endif
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jb L(more_8x_vec_backward)
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1:
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mov %RDX_LP, %RCX_LP
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rep movsb
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L(nop):
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ret
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#endif
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L(less_vec):
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/* Less than 1 VEC. */
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#if VEC_SIZE != 16 && VEC_SIZE != 32 && VEC_SIZE != 64
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# error Unsupported VEC_SIZE!
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#endif
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#if VEC_SIZE > 32
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cmpb $32, %dl
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jae L(between_32_63)
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#endif
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#if VEC_SIZE > 16
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cmpb $16, %dl
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jae L(between_16_31)
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#endif
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cmpb $8, %dl
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jae L(between_8_15)
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cmpb $4, %dl
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jae L(between_4_7)
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cmpb $1, %dl
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ja L(between_2_3)
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jb 1f
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movzbl (%rsi), %ecx
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movb %cl, (%rdi)
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1:
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ret
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#if VEC_SIZE > 32
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L(between_32_63):
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/* From 32 to 63. No branch when size == 32. */
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vmovdqu (%rsi), %ymm0
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vmovdqu -32(%rsi,%rdx), %ymm1
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vmovdqu %ymm0, (%rdi)
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vmovdqu %ymm1, -32(%rdi,%rdx)
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VZEROUPPER
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ret
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#endif
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#if VEC_SIZE > 16
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/* From 16 to 31. No branch when size == 16. */
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L(between_16_31):
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vmovdqu (%rsi), %xmm0
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vmovdqu -16(%rsi,%rdx), %xmm1
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vmovdqu %xmm0, (%rdi)
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vmovdqu %xmm1, -16(%rdi,%rdx)
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ret
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#endif
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L(between_8_15):
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/* From 8 to 15. No branch when size == 8. */
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movq -8(%rsi,%rdx), %rcx
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movq (%rsi), %rsi
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movq %rcx, -8(%rdi,%rdx)
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movq %rsi, (%rdi)
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ret
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L(between_4_7):
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/* From 4 to 7. No branch when size == 4. */
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movl -4(%rsi,%rdx), %ecx
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movl (%rsi), %esi
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movl %ecx, -4(%rdi,%rdx)
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movl %esi, (%rdi)
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ret
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L(between_2_3):
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/* From 2 to 3. No branch when size == 2. */
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movzwl -2(%rsi,%rdx), %ecx
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movzwl (%rsi), %esi
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movw %cx, -2(%rdi,%rdx)
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movw %si, (%rdi)
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ret
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#if defined USE_MULTIARCH && IS_IN (libc)
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L(movsb_more_2x_vec):
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cmpq $REP_MOVSB_THRESHOLD, %rdx
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ja L(movsb)
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#endif
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L(more_2x_vec):
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/* More than 2 * VEC and there may be overlap between destination
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and source. */
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cmpq $(VEC_SIZE * 8), %rdx
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ja L(more_8x_vec)
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cmpq $(VEC_SIZE * 4), %rdx
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jb L(last_4x_vec)
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/* Copy from 4 * VEC to 8 * VEC, inclusively. */
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VMOVU (%rsi), %VEC(0)
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VMOVU VEC_SIZE(%rsi), %VEC(1)
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VMOVU (VEC_SIZE * 2)(%rsi), %VEC(2)
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VMOVU (VEC_SIZE * 3)(%rsi), %VEC(3)
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VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(4)
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VMOVU -(VEC_SIZE * 2)(%rsi,%rdx), %VEC(5)
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VMOVU -(VEC_SIZE * 3)(%rsi,%rdx), %VEC(6)
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VMOVU -(VEC_SIZE * 4)(%rsi,%rdx), %VEC(7)
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VMOVU %VEC(0), (%rdi)
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VMOVU %VEC(1), VEC_SIZE(%rdi)
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VMOVU %VEC(2), (VEC_SIZE * 2)(%rdi)
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VMOVU %VEC(3), (VEC_SIZE * 3)(%rdi)
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VMOVU %VEC(4), -VEC_SIZE(%rdi,%rdx)
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VMOVU %VEC(5), -(VEC_SIZE * 2)(%rdi,%rdx)
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VMOVU %VEC(6), -(VEC_SIZE * 3)(%rdi,%rdx)
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VMOVU %VEC(7), -(VEC_SIZE * 4)(%rdi,%rdx)
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VZEROUPPER
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ret
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L(last_4x_vec):
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/* Copy from 2 * VEC to 4 * VEC. */
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VMOVU (%rsi), %VEC(0)
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VMOVU VEC_SIZE(%rsi), %VEC(1)
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VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(2)
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VMOVU -(VEC_SIZE * 2)(%rsi,%rdx), %VEC(3)
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VMOVU %VEC(0), (%rdi)
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VMOVU %VEC(1), VEC_SIZE(%rdi)
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VMOVU %VEC(2), -VEC_SIZE(%rdi,%rdx)
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VMOVU %VEC(3), -(VEC_SIZE * 2)(%rdi,%rdx)
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VZEROUPPER
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ret
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L(more_8x_vec):
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cmpq %rsi, %rdi
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ja L(more_8x_vec_backward)
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/* Source == destination is less common. */
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je L(nop)
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/* Load the first VEC and last 4 * VEC to support overlapping
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addresses. */
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VMOVU (%rsi), %VEC(4)
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VMOVU -VEC_SIZE(%rsi, %rdx), %VEC(5)
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %VEC(6)
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VMOVU -(VEC_SIZE * 3)(%rsi, %rdx), %VEC(7)
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VMOVU -(VEC_SIZE * 4)(%rsi, %rdx), %VEC(8)
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/* Save start and stop of the destination buffer. */
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movq %rdi, %r11
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leaq -VEC_SIZE(%rdi, %rdx), %rcx
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/* Align destination for aligned stores in the loop. Compute
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how much destination is misaligned. */
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movq %rdi, %r8
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andq $(VEC_SIZE - 1), %r8
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/* Get the negative of offset for alignment. */
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subq $VEC_SIZE, %r8
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/* Adjust source. */
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subq %r8, %rsi
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|
/* Adjust destination which should be aligned now. */
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|
subq %r8, %rdi
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|
/* Adjust length. */
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|
addq %r8, %rdx
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#if (defined USE_MULTIARCH || VEC_SIZE == 16) && IS_IN (libc)
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|
/* Check non-temporal store threshold. */
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cmpq __x86_shared_non_temporal_threshold(%rip), %rdx
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ja L(large_forward)
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|
#endif
|
|
L(loop_4x_vec_forward):
|
|
/* Copy 4 * VEC a time forward. */
|
|
VMOVU (%rsi), %VEC(0)
|
|
VMOVU VEC_SIZE(%rsi), %VEC(1)
|
|
VMOVU (VEC_SIZE * 2)(%rsi), %VEC(2)
|
|
VMOVU (VEC_SIZE * 3)(%rsi), %VEC(3)
|
|
addq $(VEC_SIZE * 4), %rsi
|
|
subq $(VEC_SIZE * 4), %rdx
|
|
VMOVA %VEC(0), (%rdi)
|
|
VMOVA %VEC(1), VEC_SIZE(%rdi)
|
|
VMOVA %VEC(2), (VEC_SIZE * 2)(%rdi)
|
|
VMOVA %VEC(3), (VEC_SIZE * 3)(%rdi)
|
|
addq $(VEC_SIZE * 4), %rdi
|
|
cmpq $(VEC_SIZE * 4), %rdx
|
|
ja L(loop_4x_vec_forward)
|
|
/* Store the last 4 * VEC. */
|
|
VMOVU %VEC(5), (%rcx)
|
|
VMOVU %VEC(6), -VEC_SIZE(%rcx)
|
|
VMOVU %VEC(7), -(VEC_SIZE * 2)(%rcx)
|
|
VMOVU %VEC(8), -(VEC_SIZE * 3)(%rcx)
|
|
/* Store the first VEC. */
|
|
VMOVU %VEC(4), (%r11)
|
|
VZEROUPPER
|
|
ret
|
|
|
|
L(more_8x_vec_backward):
|
|
/* Load the first 4 * VEC and last VEC to support overlapping
|
|
addresses. */
|
|
VMOVU (%rsi), %VEC(4)
|
|
VMOVU VEC_SIZE(%rsi), %VEC(5)
|
|
VMOVU (VEC_SIZE * 2)(%rsi), %VEC(6)
|
|
VMOVU (VEC_SIZE * 3)(%rsi), %VEC(7)
|
|
VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(8)
|
|
/* Save stop of the destination buffer. */
|
|
leaq -VEC_SIZE(%rdi, %rdx), %r11
|
|
/* Align destination end for aligned stores in the loop. Compute
|
|
how much destination end is misaligned. */
|
|
leaq -VEC_SIZE(%rsi, %rdx), %rcx
|
|
movq %r11, %r9
|
|
movq %r11, %r8
|
|
andq $(VEC_SIZE - 1), %r8
|
|
/* Adjust source. */
|
|
subq %r8, %rcx
|
|
/* Adjust the end of destination which should be aligned now. */
|
|
subq %r8, %r9
|
|
/* Adjust length. */
|
|
subq %r8, %rdx
|
|
#if (defined USE_MULTIARCH || VEC_SIZE == 16) && IS_IN (libc)
|
|
/* Check non-temporal store threshold. */
|
|
cmpq __x86_shared_non_temporal_threshold(%rip), %rdx
|
|
ja L(large_backward)
|
|
#endif
|
|
L(loop_4x_vec_backward):
|
|
/* Copy 4 * VEC a time backward. */
|
|
VMOVU (%rcx), %VEC(0)
|
|
VMOVU -VEC_SIZE(%rcx), %VEC(1)
|
|
VMOVU -(VEC_SIZE * 2)(%rcx), %VEC(2)
|
|
VMOVU -(VEC_SIZE * 3)(%rcx), %VEC(3)
|
|
subq $(VEC_SIZE * 4), %rcx
|
|
subq $(VEC_SIZE * 4), %rdx
|
|
VMOVA %VEC(0), (%r9)
|
|
VMOVA %VEC(1), -VEC_SIZE(%r9)
|
|
VMOVA %VEC(2), -(VEC_SIZE * 2)(%r9)
|
|
VMOVA %VEC(3), -(VEC_SIZE * 3)(%r9)
|
|
subq $(VEC_SIZE * 4), %r9
|
|
cmpq $(VEC_SIZE * 4), %rdx
|
|
ja L(loop_4x_vec_backward)
|
|
/* Store the first 4 * VEC. */
|
|
VMOVU %VEC(4), (%rdi)
|
|
VMOVU %VEC(5), VEC_SIZE(%rdi)
|
|
VMOVU %VEC(6), (VEC_SIZE * 2)(%rdi)
|
|
VMOVU %VEC(7), (VEC_SIZE * 3)(%rdi)
|
|
/* Store the last VEC. */
|
|
VMOVU %VEC(8), (%r11)
|
|
VZEROUPPER
|
|
ret
|
|
|
|
#if (defined USE_MULTIARCH || VEC_SIZE == 16) && IS_IN (libc)
|
|
L(large_forward):
|
|
/* Don't use non-temporal store if there is overlap between
|
|
destination and source since destination may be in cache
|
|
when source is loaded. */
|
|
leaq (%rdi, %rdx), %r10
|
|
cmpq %r10, %rsi
|
|
jb L(loop_4x_vec_forward)
|
|
L(loop_large_forward):
|
|
/* Copy 4 * VEC a time forward with non-temporal stores. */
|
|
PREFETCH_ONE_SET (1, (%rsi), PREFETCHED_LOAD_SIZE * 2)
|
|
PREFETCH_ONE_SET (1, (%rsi), PREFETCHED_LOAD_SIZE * 3)
|
|
VMOVU (%rsi), %VEC(0)
|
|
VMOVU VEC_SIZE(%rsi), %VEC(1)
|
|
VMOVU (VEC_SIZE * 2)(%rsi), %VEC(2)
|
|
VMOVU (VEC_SIZE * 3)(%rsi), %VEC(3)
|
|
addq $PREFETCHED_LOAD_SIZE, %rsi
|
|
subq $PREFETCHED_LOAD_SIZE, %rdx
|
|
VMOVNT %VEC(0), (%rdi)
|
|
VMOVNT %VEC(1), VEC_SIZE(%rdi)
|
|
VMOVNT %VEC(2), (VEC_SIZE * 2)(%rdi)
|
|
VMOVNT %VEC(3), (VEC_SIZE * 3)(%rdi)
|
|
addq $PREFETCHED_LOAD_SIZE, %rdi
|
|
cmpq $PREFETCHED_LOAD_SIZE, %rdx
|
|
ja L(loop_large_forward)
|
|
sfence
|
|
/* Store the last 4 * VEC. */
|
|
VMOVU %VEC(5), (%rcx)
|
|
VMOVU %VEC(6), -VEC_SIZE(%rcx)
|
|
VMOVU %VEC(7), -(VEC_SIZE * 2)(%rcx)
|
|
VMOVU %VEC(8), -(VEC_SIZE * 3)(%rcx)
|
|
/* Store the first VEC. */
|
|
VMOVU %VEC(4), (%r11)
|
|
VZEROUPPER
|
|
ret
|
|
|
|
L(large_backward):
|
|
/* Don't use non-temporal store if there is overlap between
|
|
destination and source since destination may be in cache
|
|
when source is loaded. */
|
|
leaq (%rcx, %rdx), %r10
|
|
cmpq %r10, %r9
|
|
jb L(loop_4x_vec_backward)
|
|
L(loop_large_backward):
|
|
/* Copy 4 * VEC a time backward with non-temporal stores. */
|
|
PREFETCH_ONE_SET (-1, (%rcx), -PREFETCHED_LOAD_SIZE * 2)
|
|
PREFETCH_ONE_SET (-1, (%rcx), -PREFETCHED_LOAD_SIZE * 3)
|
|
VMOVU (%rcx), %VEC(0)
|
|
VMOVU -VEC_SIZE(%rcx), %VEC(1)
|
|
VMOVU -(VEC_SIZE * 2)(%rcx), %VEC(2)
|
|
VMOVU -(VEC_SIZE * 3)(%rcx), %VEC(3)
|
|
subq $PREFETCHED_LOAD_SIZE, %rcx
|
|
subq $PREFETCHED_LOAD_SIZE, %rdx
|
|
VMOVNT %VEC(0), (%r9)
|
|
VMOVNT %VEC(1), -VEC_SIZE(%r9)
|
|
VMOVNT %VEC(2), -(VEC_SIZE * 2)(%r9)
|
|
VMOVNT %VEC(3), -(VEC_SIZE * 3)(%r9)
|
|
subq $PREFETCHED_LOAD_SIZE, %r9
|
|
cmpq $PREFETCHED_LOAD_SIZE, %rdx
|
|
ja L(loop_large_backward)
|
|
sfence
|
|
/* Store the first 4 * VEC. */
|
|
VMOVU %VEC(4), (%rdi)
|
|
VMOVU %VEC(5), VEC_SIZE(%rdi)
|
|
VMOVU %VEC(6), (VEC_SIZE * 2)(%rdi)
|
|
VMOVU %VEC(7), (VEC_SIZE * 3)(%rdi)
|
|
/* Store the last VEC. */
|
|
VMOVU %VEC(8), (%r11)
|
|
VZEROUPPER
|
|
ret
|
|
#endif
|
|
END (MEMMOVE_SYMBOL (__memmove, unaligned_erms))
|
|
|
|
#if IS_IN (libc)
|
|
# ifdef USE_MULTIARCH
|
|
strong_alias (MEMMOVE_SYMBOL (__memmove, unaligned_erms),
|
|
MEMMOVE_SYMBOL (__memcpy, unaligned_erms))
|
|
# ifdef SHARED
|
|
strong_alias (MEMMOVE_SYMBOL (__memmove_chk, unaligned_erms),
|
|
MEMMOVE_SYMBOL (__memcpy_chk, unaligned_erms))
|
|
# endif
|
|
# endif
|
|
# ifdef SHARED
|
|
strong_alias (MEMMOVE_CHK_SYMBOL (__memmove_chk, unaligned),
|
|
MEMMOVE_CHK_SYMBOL (__memcpy_chk, unaligned))
|
|
# endif
|
|
#endif
|
|
strong_alias (MEMMOVE_SYMBOL (__memmove, unaligned),
|
|
MEMCPY_SYMBOL (__memcpy, unaligned))
|