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Fix powerpc64 ceil, rint etc. on sNaN input (bug 20160).

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The powerpc64 versions of ceil, floor, round, trunc, rint, nearbyint
and their float versions return sNaN for sNaN input when they should
return qNaN.  This patch fixes them to add a NaN argument to itself to
quiet sNaNs before returning.

Tested for powerpc64.

	[BZ #20160]
	* sysdeps/powerpc/powerpc64/fpu/s_ceil.S (__ceil): Add NaN
	argument to itself before returning the result.
	* sysdeps/powerpc/powerpc64/fpu/s_ceilf.S (__ceilf): Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_floor.S (__floor): Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_floorf.S (__floorf): Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_nearbyint.S (__nearbyint):
	Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_nearbyintf.S (__nearbyintf):
	Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_rint.S (__rint): Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_rintf.S (__rintf): Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_round.S (__round): Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_roundf.S (__roundf): Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_trunc.S (__trunc): Likewise.
	* sysdeps/powerpc/powerpc64/fpu/s_truncf.S (__truncf): Likewise.
This commit is contained in:
Joseph Myers 2016-05-27 17:47:54 +00:00
parent debf7618f6
commit f6ef0657e4
13 changed files with 101 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
ChangeLog
View File

@ -1,5 +1,22 @@
2016-05-27 Joseph Myers <joseph@codesourcery.com>
[BZ #20160]
* sysdeps/powerpc/powerpc64/fpu/s_ceil.S (__ceil): Add NaN
argument to itself before returning the result.
* sysdeps/powerpc/powerpc64/fpu/s_ceilf.S (__ceilf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_floor.S (__floor): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_floorf.S (__floorf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_nearbyint.S (__nearbyint):
Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_nearbyintf.S (__nearbyintf):
Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_rint.S (__rint): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_rintf.S (__rintf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_round.S (__round): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_roundf.S (__roundf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_trunc.S (__trunc): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_truncf.S (__truncf): Likewise.
[BZ #20160]
* sysdeps/powerpc/powerpc32/fpu/s_ceil.S (__ceil): Add NaN
argument to itself before returning the result.

8
sysdeps/powerpc/powerpc64/fpu/s_ceil.S
View File

@ -33,7 +33,7 @@ EALIGN (__ceil, 4, 0)
mffs fp11 /* Save current FPU rounding mode and
"inexact" state. */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr- cr7
bnl- cr7,.L10
mtfsfi 7,2 /* Set rounding mode toward +inf. */
ble- cr6,.L4
fadd fp1,fp1,fp13 /* x+= TWO52; */
@ -53,6 +53,12 @@ EALIGN (__ceil, 4, 0)
mtfsf 0xff,fp11 /* Restore previous rounding mode and
"inexact" state. */
blr
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadd fp1,fp1,fp1
blr
END (__ceil)
weak_alias (__ceil, ceil)

8
sysdeps/powerpc/powerpc64/fpu/s_ceilf.S
View File

@ -34,7 +34,7 @@ EALIGN (__ceilf, 4, 0)
mffs fp11 /* Save current FPU rounding mode and
"inexact" state. */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr- cr7
bnl- cr7,.L10
mtfsfi 7,2 /* Set rounding mode toward +inf. */
ble- cr6,.L4
fadds fp1,fp1,fp13 /* x+= TWO23; */
@ -54,6 +54,12 @@ EALIGN (__ceilf, 4, 0)
mtfsf 0xff,fp11 /* Restore previous rounding mode and
"inexact" state. */
blr
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadds fp1,fp1,fp1
blr
END (__ceilf)
weak_alias (__ceilf, ceilf)

8
sysdeps/powerpc/powerpc64/fpu/s_floor.S
View File

@ -33,7 +33,7 @@ EALIGN (__floor, 4, 0)
mffs fp11 /* Save current FPU rounding mode and
"inexact" state. */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr- cr7
bnl- cr7,.L10
mtfsfi 7,3 /* Set rounding mode toward -inf. */
ble- cr6,.L4
fadd fp1,fp1,fp13 /* x+= TWO52; */
@ -53,6 +53,12 @@ EALIGN (__floor, 4, 0)
mtfsf 0xff,fp11 /* Restore previous rounding mode and
"inexact" state. */
blr
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadd fp1,fp1,fp1
blr
END (__floor)
weak_alias (__floor, floor)

8
sysdeps/powerpc/powerpc64/fpu/s_floorf.S
View File

@ -34,7 +34,7 @@ EALIGN (__floorf, 4, 0)
mffs fp11 /* Save current FPU rounding mode and
"inexact" state. */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr- cr7
bnl- cr7,.L10
mtfsfi 7,3 /* Set rounding mode toward -inf. */
ble- cr6,.L4
fadds fp1,fp1,fp13 /* x+= TWO23; */
@ -54,6 +54,12 @@ EALIGN (__floorf, 4, 0)
mtfsf 0xff,fp11 /* Restore previous rounding mode and
"inexact" state. */
blr
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadds fp1,fp1,fp1
blr
END (__floorf)
weak_alias (__floorf, floorf)

8
sysdeps/powerpc/powerpc64/fpu/s_nearbyint.S
View File

@ -36,7 +36,7 @@ EALIGN (__nearbyint, 4, 0)
fabs fp0,fp1
lfd fp13,.LC0@toc(2)
fcmpu cr7,fp0,fp13 /* if (fabs(x) > TWO52) */
bgelr cr7
bge cr7,.L10
fsub fp12,fp13,fp13 /* generate 0.0 */
fcmpu cr7,fp1,fp12 /* if (x > 0.0) */
ble cr7, L(lessthanzero)
@ -56,6 +56,12 @@ L(lessthanzero):
fnabs fp1,fp1 /* if (x == 0.0) */
mtfsf 0xff,fp11 /* Restore FE_INEXACT state. */
blr /* x = -0.0; */
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadd fp1,fp1,fp1
blr
END (__nearbyint)
weak_alias (__nearbyint, nearbyint)

8
sysdeps/powerpc/powerpc64/fpu/s_nearbyintf.S
View File

@ -37,7 +37,7 @@ EALIGN (__nearbyintf, 4, 0)
fabs fp0,fp1
lfs fp13,.LC0@toc(2)
fcmpu cr7,fp0,fp13 /* if (fabs(x) > TWO52) */
bgelr cr7
bge cr7,.L10
fsubs fp12,fp13,fp13 /* generate 0.0 */
fcmpu cr7,fp1,fp12 /* if (x > 0.0) */
ble cr7, L(lessthanzero)
@ -57,6 +57,12 @@ L(lessthanzero):
fnabs fp1,fp1 /* if (x == 0.0) */
mtfsf 0xff,fp11 /* Restore FE_INEXACT state. */
blr /* x = -0.0; */
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadds fp1,fp1,fp1
blr
END (__nearbyintf)
weak_alias (__nearbyintf, nearbyintf)

8
sysdeps/powerpc/powerpc64/fpu/s_rint.S
View File

@ -34,7 +34,7 @@ EALIGN (__rint, 4, 0)
fsub fp12,fp13,fp13 /* generate 0.0 */
fcmpu cr7,fp0,fp13 /* if (fabs(x) > TWO52) */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr cr7
bnl cr7,.L10
bng cr6,.L4
fadd fp1,fp1,fp13 /* x+= TWO52; */
fsub fp1,fp1,fp13 /* x-= TWO52; */
@ -46,6 +46,12 @@ EALIGN (__rint, 4, 0)
fadd fp1,fp1,fp13 /* x+= TWO52; */
fnabs fp1,fp1 /* if (x == 0.0) */
blr /* x = -0.0; */
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadd fp1,fp1,fp1
blr
END (__rint)
weak_alias (__rint, rint)

8
sysdeps/powerpc/powerpc64/fpu/s_rintf.S
View File

@ -32,7 +32,7 @@ EALIGN (__rintf, 4, 0)
fsubs fp12,fp13,fp13 /* generate 0.0 */
fcmpu cr7,fp0,fp13 /* if (fabs(x) > TWO23) */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr cr7
bnl cr7,.L10
bng cr6,.L4
fadds fp1,fp1,fp13 /* x+= TWO23; */
fsubs fp1,fp1,fp13 /* x-= TWO23; */
@ -44,6 +44,12 @@ EALIGN (__rintf, 4, 0)
fadds fp1,fp1,fp13 /* x+= TWO23; */
fnabs fp1,fp1 /* if (x == 0.0) */
blr /* x = -0.0; */
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadds fp1,fp1,fp1
blr
END (__rintf)
weak_alias (__rintf, rintf)

8
sysdeps/powerpc/powerpc64/fpu/s_round.S
View File

@ -45,7 +45,7 @@ EALIGN (__round, 4, 0)
mffs fp11 /* Save current FPU rounding mode and
"inexact" state. */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr- cr7
bnl- cr7,.L10
mtfsfi 7,1 /* Set rounding mode toward 0. */
lfd fp10,.LC1@toc(2)
ble- cr6,.L4
@ -68,6 +68,12 @@ EALIGN (__round, 4, 0)
mtfsf 0xff,fp11 /* Restore previous rounding mode and
"inexact" state. */
blr
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadd fp1,fp1,fp1
blr
END (__round)
weak_alias (__round, round)

8
sysdeps/powerpc/powerpc64/fpu/s_roundf.S
View File

@ -46,7 +46,7 @@ EALIGN (__roundf, 4, 0)
mffs fp11 /* Save current FPU rounding mode and
"inexact" state. */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr- cr7
bnl- cr7,.L10
mtfsfi 7,1 /* Set rounding mode toward 0. */
lfs fp10,.LC1@toc(2)
ble- cr6,.L4
@ -69,6 +69,12 @@ EALIGN (__roundf, 4, 0)
mtfsf 0xff,fp11 /* Restore previous rounding mode and
"inexact" state. */
blr
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadds fp1,fp1,fp1
blr
END (__roundf)
weak_alias (__roundf, roundf)

8
sysdeps/powerpc/powerpc64/fpu/s_trunc.S
View File

@ -40,7 +40,7 @@ EALIGN (__trunc, 4, 0)
mffs fp11 /* Save current FPU rounding mode and
"inexact" state. */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr- cr7
bnl- cr7,.L10
mtfsfi 7,1 /* Set rounding toward 0 mode. */
ble- cr6,.L4
fadd fp1,fp1,fp13 /* x+= TWO52; */
@ -60,6 +60,12 @@ EALIGN (__trunc, 4, 0)
mtfsf 0xff,fp11 /* Restore previous rounding mode and
"inexact" state. */
blr
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadd fp1,fp1,fp1
blr
END (__trunc)
weak_alias (__trunc, trunc)

8
sysdeps/powerpc/powerpc64/fpu/s_truncf.S
View File

@ -41,7 +41,7 @@ EALIGN (__truncf, 4, 0)
mffs fp11 /* Save current FPU rounding mode and
"inexact" state. */
fcmpu cr6,fp1,fp12 /* if (x > 0.0) */
bnllr- cr7
bnl- cr7,.L10
mtfsfi 7,1 /* Set rounding toward 0 mode. */
ble- cr6,.L4
fadds fp1,fp1,fp13 /* x+= TWO23; */
@ -61,6 +61,12 @@ EALIGN (__truncf, 4, 0)
mtfsf 0xff,fp11 /* Restore previous rounding mode and
"inexact" state. */
blr
.L10:
/* Ensure sNaN input is converted to qNaN. */
fcmpu cr7,fp1,fp1
beqlr cr7
fadds fp1,fp1,fp1
blr
END (__truncf)
weak_alias (__truncf, truncf)