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git://sourceware.org/git/glibc.git
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2012-10-31 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/memcpy.S: Add prefetching and more unrolling, make it work in 32 or 64 bit modes. * sysdeps/mips/mips64/memcpy.S: Remove.
This commit is contained in:
Steve Ellcey
parent
ef82f4da79
commit
e6ff7f84f7
@ -1,3 +1,9 @@
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2012-10-31 Steve Ellcey <sellcey@mips.com>
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* sysdeps/mips/memcpy.S: Add prefetching and more unrolling, make
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it work in 32 or 64 bit modes.
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* sysdeps/mips/mips64/memcpy.S: Remove.
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2012-10-30 Joseph Myers <joseph@codesourcery.com>
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[BZ #14047]
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@ -1,7 +1,8 @@
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/* Copyright (C) 2002-2012 Free Software Foundation, Inc.
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/* Copyright (C) 2012 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Hartvig Ekner <hartvige@mips.com>, 2002.
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Contributed by MIPS Technologies, Inc.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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@ -16,119 +17,616 @@
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifdef ANDROID_CHANGES
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#include "machine/asm.h"
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#include "machine/regdef.h"
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#define USE_MEMMOVE_FOR_OVERLAP
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#define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED
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#define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
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#elif _LIBC
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#include <sysdep.h>
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/* void *memcpy(void *s1, const void *s2, size_t n); */
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#if __MIPSEB
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# define LWHI lwl /* high part is left in big-endian */
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# define SWHI swl /* high part is left in big-endian */
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# define LWLO lwr /* low part is right in big-endian */
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# define SWLO swr /* low part is right in big-endian */
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#include <regdef.h>
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#include <sys/asm.h>
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#define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED
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#define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED
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#elif _COMPILING_NEWLIB
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#include "machine/asm.h"
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#include "machine/regdef.h"
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#define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED
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#define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED
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#else
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# define LWHI lwr /* high part is right in little-endian */
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# define SWHI swr /* high part is right in little-endian */
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# define LWLO lwl /* low part is left in little-endian */
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# define SWLO swl /* low part is left in little-endian */
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#include <regdef.h>
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#include <sys/asm.h>
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#endif
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ENTRY (memcpy)
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#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
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(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
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#ifndef DISABLE_PREFETCH
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#define USE_PREFETCH
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#endif
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#endif
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#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)
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#ifndef DISABLE_DOUBLE
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#define USE_DOUBLE
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#endif
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#endif
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/* Some asm.h files do not have the L macro definition. */
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#ifndef L
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#if _MIPS_SIM == _ABIO32
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# define L(label) $L ## label
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#else
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# define L(label) .L ## label
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#endif
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#endif
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/* Some asm.h files do not have the PTR_ADDIU macro definition. */
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#ifndef PTR_ADDIU
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#ifdef USE_DOUBLE
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#define PTR_ADDIU daddiu
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#else
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#define PTR_ADDIU addiu
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#endif
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#endif
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/* Some asm.h files do not have the PTR_SRA macro definition. */
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#ifndef PTR_SRA
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#ifdef USE_DOUBLE
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#define PTR_SRA dsra
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#else
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#define PTR_SRA sra
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#endif
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#endif
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/*
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* Using PREFETCH_HINT_LOAD_STREAMED instead of PREFETCH_LOAD on load
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* prefetches appears to offer a slight preformance advantage.
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*
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* Using PREFETCH_HINT_PREPAREFORSTORE instead of PREFETCH_STORE
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* or PREFETCH_STORE_STREAMED offers a large performance advantage
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* but PREPAREFORSTORE has some special restrictions to consider.
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*
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* Prefetch with the 'prepare for store' hint does not copy a memory
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* location into the cache, it just allocates a cache line and zeros
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* it out. This means that if you do not write to the entire cache
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* line before writing it out to memory some data will get zero'ed out
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* when the cache line is written back to memory and data will be lost.
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*
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* Also if you are using this memcpy to copy overlapping buffers it may
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* not behave correctly when using the 'prepare for store' hint. If you
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* use the 'prepare for store' prefetch on a memory area that is in the
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* memcpy source (as well as the memcpy destination), then you will get
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* some data zero'ed out before you have a chance to read it and data will
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* be lost.
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*
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* If you are going to use this memcpy routine with the 'prepare for store'
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* prefetch you may want to set USE_MEMMOVE_FOR_OVERLAP in order to avoid
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* the problem of running memcpy on overlapping buffers.
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*
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* There are ifdef'ed sections of this memcpy to make sure that it does not
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* do prefetches on cache lines that are not going to be completely written.
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* This code is only needed and only used when PREFETCH_STORE_HINT is set to
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* PREFETCH_HINT_PREPAREFORSTORE. This code assumes that cache lines are
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* 32 bytes and if the cache line is larger it will not work correctly.
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*/
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#ifdef USE_PREFETCH
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# define PREFETCH_HINT_LOAD 0
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# define PREFETCH_HINT_STORE 1
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# define PREFETCH_HINT_LOAD_STREAMED 4
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# define PREFETCH_HINT_STORE_STREAMED 5
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# define PREFETCH_HINT_LOAD_RETAINED 6
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# define PREFETCH_HINT_STORE_RETAINED 7
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# define PREFETCH_HINT_WRITEBACK_INVAL 25
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# define PREFETCH_HINT_PREPAREFORSTORE 30
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/*
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* If we have not picked out what hints to use at this point use the
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* standard load and store prefetch hints.
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*/
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#ifndef PREFETCH_STORE_HINT
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# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE
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#endif
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#ifndef PREFETCH_LOAD_HINT
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# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD
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#endif
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/*
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* We double everything when USE_DOUBLE is true so we do 2 prefetches to
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* get 64 bytes in that case. The assumption is that each individual
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* prefetch brings in 32 bytes.
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*/
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#ifdef USE_DOUBLE
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# define PREFETCH_CHUNK 64
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# define PREFETCH_FOR_LOAD(chunk, reg) \
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pref PREFETCH_LOAD_HINT, (chunk)*32(reg); \
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pref PREFETCH_LOAD_HINT, ((chunk)+1)*32(reg)
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# define PREFETCH_FOR_STORE(chunk, reg) \
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pref PREFETCH_STORE_HINT, (chunk)*32(reg); \
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pref PREFETCH_STORE_HINT, ((chunk)+1)*32(reg)
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#else
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# define PREFETCH_CHUNK 32
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# define PREFETCH_FOR_LOAD(chunk, reg) \
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pref PREFETCH_LOAD_HINT, (chunk)*32(reg)
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# define PREFETCH_FOR_STORE(chunk, reg) \
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pref PREFETCH_STORE_HINT, (chunk)*32(reg)
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#endif
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# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK)
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#else /* USE_PREFETCH not defined */
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# define PREFETCH_FOR_LOAD(offset, reg)
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# define PREFETCH_FOR_STORE(offset, reg)
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#endif
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/* Allow the routine to be named something else if desired. */
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#ifndef MEMCPY_NAME
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#define MEMCPY_NAME memcpy
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#endif
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/* We use these 32/64 bit registers as temporaries to do the copying. */
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#define REG0 t0
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#define REG1 t1
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#define REG2 t2
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#define REG3 t3
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#if _MIPS_SIM == _ABIO32
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# define REG4 t4
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# define REG5 t5
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# define REG6 t6
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# define REG7 t7
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#else
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# define REG4 ta0
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# define REG5 ta1
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# define REG6 ta2
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# define REG7 ta3
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#endif
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/* We load/store 64 bits at a time when USE_DOUBLE is true.
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* The C_ prefix stands for CHUNK and is used to avoid macro name
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* conflicts with system header files. */
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#ifdef USE_DOUBLE
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# define C_ST sd
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# define C_LD ld
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#if __MIPSEB
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# define C_LDHI ldl /* high part is left in big-endian */
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# define C_STHI sdl /* high part is left in big-endian */
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# define C_LDLO ldr /* low part is right in big-endian */
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# define C_STLO sdr /* low part is right in big-endian */
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#else
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# define C_LDHI ldr /* high part is right in little-endian */
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# define C_STHI sdr /* high part is right in little-endian */
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# define C_LDLO ldl /* low part is left in little-endian */
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# define C_STLO sdl /* low part is left in little-endian */
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#endif
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#else
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# define C_ST sw
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# define C_LD lw
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#if __MIPSEB
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# define C_LDHI lwl /* high part is left in big-endian */
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# define C_STHI swl /* high part is left in big-endian */
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# define C_LDLO lwr /* low part is right in big-endian */
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# define C_STLO swr /* low part is right in big-endian */
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#else
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# define C_LDHI lwr /* high part is right in little-endian */
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# define C_STHI swr /* high part is right in little-endian */
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# define C_LDLO lwl /* low part is left in little-endian */
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# define C_STLO swl /* low part is left in little-endian */
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#endif
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#endif
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/* Bookkeeping values for 32 vs. 64 bit mode. */
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#ifdef USE_DOUBLE
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# define NSIZE 8
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# define NSIZEMASK 0x3f
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# define NSIZEDMASK 0x7f
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#else
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# define NSIZE 4
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# define NSIZEMASK 0x1f
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# define NSIZEDMASK 0x3f
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#endif
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#define UNIT(unit) ((unit)*NSIZE)
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#define UNITM1(unit) (((unit)*NSIZE)-1)
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#ifdef ANDROID_CHANGES
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LEAF(MEMCPY_NAME, 0)
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#else
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LEAF(MEMCPY_NAME)
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#endif
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.set nomips16
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.set noreorder
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/*
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* Below we handle the case where memcpy is called with overlapping src and dst.
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* Although memcpy is not required to handle this case, some parts of Android
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* like Skia rely on such usage. We call memmove to handle such cases.
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*/
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#ifdef USE_MEMMOVE_FOR_OVERLAP
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PTR_SUBU t0,a0,a1
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PTR_SRA t2,t0,31
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xor t1,t0,t2
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PTR_SUBU t0,t1,t2
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sltu t2,t0,a2
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beq t2,zero,L(memcpy)
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la t9,memmove
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jr t9
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nop
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L(memcpy):
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#endif
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/*
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* If the size is less then 2*NSIZE (8 or 16), go to L(lastb). Regardless of
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* size, copy dst pointer to v0 for the return value.
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*/
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slti t2,a2,(2 * NSIZE)
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bne t2,zero,L(lastb)
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move v0,a0
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/*
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* If src and dst have different alignments, go to L(unaligned), if they
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* have the same alignment (but are not actually aligned) do a partial
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* load/store to make them aligned. If they are both already aligned
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* we can start copying at L(aligned).
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*/
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xor t8,a1,a0
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andi t8,t8,(NSIZE-1) /* t8 is a0/a1 word-displacement */
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bne t8,zero,L(unaligned)
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PTR_SUBU a3, zero, a0
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slti t0, a2, 8 # Less than 8?
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bne t0, zero, L(last8)
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move v0, a0 # Setup exit value before too late
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andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */
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beq a3,zero,L(aligned) /* if a3=0, it is already aligned */
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PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */
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xor t0, a1, a0 # Find a0/a1 displacement
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andi t0, 0x3
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bne t0, zero, L(shift) # Go handle the unaligned case
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subu t1, zero, a1
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andi t1, 0x3 # a0/a1 are aligned, but are we
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beq t1, zero, L(chk8w) # starting in the middle of a word?
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subu a2, t1
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LWHI t0, 0(a1) # Yes we are... take care of that
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addu a1, t1
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SWHI t0, 0(a0)
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addu a0, t1
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C_LDHI t8,0(a1)
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PTR_ADDU a1,a1,a3
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C_STHI t8,0(a0)
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PTR_ADDU a0,a0,a3
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L(chk8w):
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andi t0, a2, 0x1f # 32 or more bytes left?
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beq t0, a2, L(chk1w)
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subu a3, a2, t0 # Yes
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addu a3, a1 # a3 = end address of loop
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move a2, t0 # a2 = what will be left after loop
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L(lop8w):
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lw t0, 0(a1) # Loop taking 8 words at a time
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lw t1, 4(a1)
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lw t2, 8(a1)
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lw t3, 12(a1)
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lw t4, 16(a1)
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lw t5, 20(a1)
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lw t6, 24(a1)
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lw t7, 28(a1)
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addiu a0, 32
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addiu a1, 32
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sw t0, -32(a0)
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sw t1, -28(a0)
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sw t2, -24(a0)
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sw t3, -20(a0)
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sw t4, -16(a0)
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sw t5, -12(a0)
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sw t6, -8(a0)
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bne a1, a3, L(lop8w)
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sw t7, -4(a0)
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/*
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* Now dst/src are both aligned to (word or double word) aligned addresses
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* Set a2 to count how many bytes we have to copy after all the 64/128 byte
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* chunks are copied and a3 to the dst pointer after all the 64/128 byte
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* chunks have been copied. We will loop, incrementing a0 and a1 until a0
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* equals a3.
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*/
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L(chk1w):
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andi t0, a2, 0x3 # 4 or more bytes left?
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beq t0, a2, L(last8)
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subu a3, a2, t0 # Yes, handle them one word at a time
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addu a3, a1 # a3 again end address
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move a2, t0
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L(lop1w):
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lw t0, 0(a1)
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addiu a0, 4
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addiu a1, 4
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bne a1, a3, L(lop1w)
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sw t0, -4(a0)
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L(aligned):
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andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */
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beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */
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PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */
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PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
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L(last8):
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blez a2, L(lst8e) # Handle last 8 bytes, one at a time
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addu a3, a2, a1
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L(lst8l):
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lb t0, 0(a1)
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addiu a0, 1
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addiu a1, 1
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bne a1, a3, L(lst8l)
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sb t0, -1(a0)
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L(lst8e):
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jr ra # Bye, bye
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/* When in the loop we may prefetch with the 'prepare to store' hint,
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* in this case the a0+x should not be past the "t0-32" address. This
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* means: for x=128 the last "safe" a0 address is "t0-160". Alternatively,
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* for x=64 the last "safe" a0 address is "t0-96" In the current version we
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* will use "prefetch hint,128(a0)", so "t0-160" is the limit.
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*/
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
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PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */
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#endif
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PREFETCH_FOR_LOAD (0, a1)
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PREFETCH_FOR_LOAD (1, a1)
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PREFETCH_FOR_LOAD (2, a1)
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PREFETCH_FOR_STORE (1, a0)
|
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */
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bgtz v1,L(loop16w)
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nop
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#endif
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PREFETCH_FOR_STORE (2, a0)
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L(loop16w):
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PREFETCH_FOR_LOAD (3, a1)
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C_LD t0,UNIT(0)(a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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bgtz v1,L(skip_pref30_96)
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#endif
|
||||
C_LD t1,UNIT(1)(a1)
|
||||
PREFETCH_FOR_STORE (3, a0)
|
||||
L(skip_pref30_96):
|
||||
C_LD REG2,UNIT(2)(a1)
|
||||
C_LD REG3,UNIT(3)(a1)
|
||||
C_LD REG4,UNIT(4)(a1)
|
||||
C_LD REG5,UNIT(5)(a1)
|
||||
C_LD REG6,UNIT(6)(a1)
|
||||
C_LD REG7,UNIT(7)(a1)
|
||||
PREFETCH_FOR_LOAD (4, a1)
|
||||
|
||||
C_ST t0,UNIT(0)(a0)
|
||||
C_ST t1,UNIT(1)(a0)
|
||||
C_ST REG2,UNIT(2)(a0)
|
||||
C_ST REG3,UNIT(3)(a0)
|
||||
C_ST REG4,UNIT(4)(a0)
|
||||
C_ST REG5,UNIT(5)(a0)
|
||||
C_ST REG6,UNIT(6)(a0)
|
||||
C_ST REG7,UNIT(7)(a0)
|
||||
|
||||
C_LD t0,UNIT(8)(a1)
|
||||
#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
|
||||
bgtz v1,L(skip_pref30_128)
|
||||
#endif
|
||||
C_LD t1,UNIT(9)(a1)
|
||||
PREFETCH_FOR_STORE (4, a0)
|
||||
L(skip_pref30_128):
|
||||
C_LD REG2,UNIT(10)(a1)
|
||||
C_LD REG3,UNIT(11)(a1)
|
||||
C_LD REG4,UNIT(12)(a1)
|
||||
C_LD REG5,UNIT(13)(a1)
|
||||
C_LD REG6,UNIT(14)(a1)
|
||||
C_LD REG7,UNIT(15)(a1)
|
||||
PREFETCH_FOR_LOAD (5, a1)
|
||||
C_ST t0,UNIT(8)(a0)
|
||||
C_ST t1,UNIT(9)(a0)
|
||||
C_ST REG2,UNIT(10)(a0)
|
||||
C_ST REG3,UNIT(11)(a0)
|
||||
C_ST REG4,UNIT(12)(a0)
|
||||
C_ST REG5,UNIT(13)(a0)
|
||||
C_ST REG6,UNIT(14)(a0)
|
||||
C_ST REG7,UNIT(15)(a0)
|
||||
PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
|
||||
#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
|
||||
sltu v1,t9,a0
|
||||
#endif
|
||||
bne a0,a3,L(loop16w)
|
||||
PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
|
||||
move a2,t8
|
||||
|
||||
/* Here we have src and dest word-aligned but less than 64-bytes or
|
||||
* 128 bytes to go. Check for a 32(64) byte chunk and copy if if there
|
||||
* is one. Otherwise jump down to L(chk1w) to handle the tail end of
|
||||
* the copy.
|
||||
*/
|
||||
|
||||
L(chkw):
|
||||
PREFETCH_FOR_LOAD (0, a1)
|
||||
andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */
|
||||
/* The t8 is the reminder count past 32-bytes */
|
||||
beq a2,t8,L(chk1w) /* When a2=t8, no 32-byte chunk */
|
||||
nop
|
||||
C_LD t0,UNIT(0)(a1)
|
||||
C_LD t1,UNIT(1)(a1)
|
||||
C_LD REG2,UNIT(2)(a1)
|
||||
C_LD REG3,UNIT(3)(a1)
|
||||
C_LD REG4,UNIT(4)(a1)
|
||||
C_LD REG5,UNIT(5)(a1)
|
||||
C_LD REG6,UNIT(6)(a1)
|
||||
C_LD REG7,UNIT(7)(a1)
|
||||
PTR_ADDIU a1,a1,UNIT(8)
|
||||
C_ST t0,UNIT(0)(a0)
|
||||
C_ST t1,UNIT(1)(a0)
|
||||
C_ST REG2,UNIT(2)(a0)
|
||||
C_ST REG3,UNIT(3)(a0)
|
||||
C_ST REG4,UNIT(4)(a0)
|
||||
C_ST REG5,UNIT(5)(a0)
|
||||
C_ST REG6,UNIT(6)(a0)
|
||||
C_ST REG7,UNIT(7)(a0)
|
||||
PTR_ADDIU a0,a0,UNIT(8)
|
||||
|
||||
/*
|
||||
* Here we have less then 32(64) bytes to copy. Set up for a loop to
|
||||
* copy one word (or double word) at a time. Set a2 to count how many
|
||||
* bytes we have to copy after all the word (or double word) chunks are
|
||||
* copied and a3 to the dst pointer after all the (d)word chunks have
|
||||
* been copied. We will loop, incrementing a0 and a1 until a0 equals a3.
|
||||
*/
|
||||
L(chk1w):
|
||||
andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */
|
||||
beq a2,t8,L(lastb)
|
||||
PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */
|
||||
PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
|
||||
|
||||
/* copying in words (4-byte or 8-byte chunks) */
|
||||
L(wordCopy_loop):
|
||||
C_LD REG3,UNIT(0)(a1)
|
||||
PTR_ADDIU a1,a1,UNIT(1)
|
||||
PTR_ADDIU a0,a0,UNIT(1)
|
||||
bne a0,a3,L(wordCopy_loop)
|
||||
C_ST REG3,UNIT(-1)(a0)
|
||||
|
||||
/* Copy the last 8 (or 16) bytes */
|
||||
L(lastb):
|
||||
blez a2,L(leave)
|
||||
PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
|
||||
L(lastbloop):
|
||||
lb v1,0(a1)
|
||||
PTR_ADDIU a1,a1,1
|
||||
PTR_ADDIU a0,a0,1
|
||||
bne a0,a3,L(lastbloop)
|
||||
sb v1,-1(a0)
|
||||
L(leave):
|
||||
j ra
|
||||
nop
|
||||
/*
|
||||
* UNALIGNED case, got here with a3 = "negu a0"
|
||||
* This code is nearly identical to the aligned code above
|
||||
* but only the destination (not the source) gets aligned
|
||||
* so we need to do partial loads of the source followed
|
||||
* by normal stores to the destination (once we have aligned
|
||||
* the destination).
|
||||
*/
|
||||
|
||||
L(unaligned):
|
||||
andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */
|
||||
beqz a3,L(ua_chk16w) /* if a3=0, it is already aligned */
|
||||
PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */
|
||||
|
||||
C_LDHI v1,UNIT(0)(a1)
|
||||
C_LDLO v1,UNITM1(1)(a1)
|
||||
PTR_ADDU a1,a1,a3
|
||||
C_STHI v1,UNIT(0)(a0)
|
||||
PTR_ADDU a0,a0,a3
|
||||
|
||||
/*
|
||||
* Now the destination (but not the source) is aligned
|
||||
* Set a2 to count how many bytes we have to copy after all the 64/128 byte
|
||||
* chunks are copied and a3 to the dst pointer after all the 64/128 byte
|
||||
* chunks have been copied. We will loop, incrementing a0 and a1 until a0
|
||||
* equals a3.
|
||||
*/
|
||||
|
||||
L(ua_chk16w):
|
||||
andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */
|
||||
beq a2,t8,L(ua_chkw) /* if a2==t8, no 64-byte/128-byte chunks */
|
||||
PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */
|
||||
PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
|
||||
|
||||
#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
|
||||
PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
|
||||
PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */
|
||||
#endif
|
||||
PREFETCH_FOR_LOAD (0, a1)
|
||||
PREFETCH_FOR_LOAD (1, a1)
|
||||
PREFETCH_FOR_LOAD (2, a1)
|
||||
PREFETCH_FOR_STORE (1, a0)
|
||||
#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
|
||||
sltu v1,t9,a0
|
||||
bgtz v1,L(ua_loop16w) /* skip prefetch for too short arrays */
|
||||
nop
|
||||
#endif
|
||||
PREFETCH_FOR_STORE (2, a0)
|
||||
L(ua_loop16w):
|
||||
PREFETCH_FOR_LOAD (3, a1)
|
||||
C_LDHI t0,UNIT(0)(a1)
|
||||
C_LDLO t0,UNITM1(1)(a1)
|
||||
C_LDHI t1,UNIT(1)(a1)
|
||||
#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
|
||||
bgtz v1,L(ua_skip_pref30_96)
|
||||
#endif
|
||||
C_LDLO t1,UNITM1(2)(a1)
|
||||
PREFETCH_FOR_STORE (3, a0)
|
||||
L(ua_skip_pref30_96):
|
||||
C_LDHI REG2,UNIT(2)(a1)
|
||||
C_LDLO REG2,UNITM1(3)(a1)
|
||||
C_LDHI REG3,UNIT(3)(a1)
|
||||
C_LDLO REG3,UNITM1(4)(a1)
|
||||
C_LDHI REG4,UNIT(4)(a1)
|
||||
C_LDLO REG4,UNITM1(5)(a1)
|
||||
C_LDHI REG5,UNIT(5)(a1)
|
||||
C_LDLO REG5,UNITM1(6)(a1)
|
||||
C_LDHI REG6,UNIT(6)(a1)
|
||||
C_LDLO REG6,UNITM1(7)(a1)
|
||||
C_LDHI REG7,UNIT(7)(a1)
|
||||
C_LDLO REG7,UNITM1(8)(a1)
|
||||
PREFETCH_FOR_LOAD (4, a1)
|
||||
C_ST t0,UNIT(0)(a0)
|
||||
C_ST t1,UNIT(1)(a0)
|
||||
C_ST REG2,UNIT(2)(a0)
|
||||
C_ST REG3,UNIT(3)(a0)
|
||||
C_ST REG4,UNIT(4)(a0)
|
||||
C_ST REG5,UNIT(5)(a0)
|
||||
C_ST REG6,UNIT(6)(a0)
|
||||
C_ST REG7,UNIT(7)(a0)
|
||||
C_LDHI t0,UNIT(8)(a1)
|
||||
C_LDLO t0,UNITM1(9)(a1)
|
||||
C_LDHI t1,UNIT(9)(a1)
|
||||
#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
|
||||
bgtz v1,L(ua_skip_pref30_128)
|
||||
#endif
|
||||
C_LDLO t1,UNITM1(10)(a1)
|
||||
PREFETCH_FOR_STORE (4, a0)
|
||||
L(ua_skip_pref30_128):
|
||||
C_LDHI REG2,UNIT(10)(a1)
|
||||
C_LDLO REG2,UNITM1(11)(a1)
|
||||
C_LDHI REG3,UNIT(11)(a1)
|
||||
C_LDLO REG3,UNITM1(12)(a1)
|
||||
C_LDHI REG4,UNIT(12)(a1)
|
||||
C_LDLO REG4,UNITM1(13)(a1)
|
||||
C_LDHI REG5,UNIT(13)(a1)
|
||||
C_LDLO REG5,UNITM1(14)(a1)
|
||||
C_LDHI REG6,UNIT(14)(a1)
|
||||
C_LDLO REG6,UNITM1(15)(a1)
|
||||
C_LDHI REG7,UNIT(15)(a1)
|
||||
C_LDLO REG7,UNITM1(16)(a1)
|
||||
PREFETCH_FOR_LOAD (5, a1)
|
||||
C_ST t0,UNIT(8)(a0)
|
||||
C_ST t1,UNIT(9)(a0)
|
||||
C_ST REG2,UNIT(10)(a0)
|
||||
C_ST REG3,UNIT(11)(a0)
|
||||
C_ST REG4,UNIT(12)(a0)
|
||||
C_ST REG5,UNIT(13)(a0)
|
||||
C_ST REG6,UNIT(14)(a0)
|
||||
C_ST REG7,UNIT(15)(a0)
|
||||
PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
|
||||
#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
|
||||
sltu v1,t9,a0
|
||||
#endif
|
||||
bne a0,a3,L(ua_loop16w)
|
||||
PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
|
||||
move a2,t8
|
||||
|
||||
/* Here we have src and dest word-aligned but less than 64-bytes or
|
||||
* 128 bytes to go. Check for a 32(64) byte chunk and copy if if there
|
||||
* is one. Otherwise jump down to L(ua_chk1w) to handle the tail end of
|
||||
* the copy. */
|
||||
|
||||
L(ua_chkw):
|
||||
PREFETCH_FOR_LOAD (0, a1)
|
||||
andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */
|
||||
/* t8 is the reminder count past 32-bytes */
|
||||
beq a2,t8,L(ua_chk1w) /* When a2=t8, no 32-byte chunk */
|
||||
nop
|
||||
C_LDHI t0,UNIT(0)(a1)
|
||||
C_LDLO t0,UNITM1(1)(a1)
|
||||
C_LDHI t1,UNIT(1)(a1)
|
||||
C_LDLO t1,UNITM1(2)(a1)
|
||||
C_LDHI REG2,UNIT(2)(a1)
|
||||
C_LDLO REG2,UNITM1(3)(a1)
|
||||
C_LDHI REG3,UNIT(3)(a1)
|
||||
C_LDLO REG3,UNITM1(4)(a1)
|
||||
C_LDHI REG4,UNIT(4)(a1)
|
||||
C_LDLO REG4,UNITM1(5)(a1)
|
||||
C_LDHI REG5,UNIT(5)(a1)
|
||||
C_LDLO REG5,UNITM1(6)(a1)
|
||||
C_LDHI REG6,UNIT(6)(a1)
|
||||
C_LDLO REG6,UNITM1(7)(a1)
|
||||
C_LDHI REG7,UNIT(7)(a1)
|
||||
C_LDLO REG7,UNITM1(8)(a1)
|
||||
PTR_ADDIU a1,a1,UNIT(8)
|
||||
C_ST t0,UNIT(0)(a0)
|
||||
C_ST t1,UNIT(1)(a0)
|
||||
C_ST REG2,UNIT(2)(a0)
|
||||
C_ST REG3,UNIT(3)(a0)
|
||||
C_ST REG4,UNIT(4)(a0)
|
||||
C_ST REG5,UNIT(5)(a0)
|
||||
C_ST REG6,UNIT(6)(a0)
|
||||
C_ST REG7,UNIT(7)(a0)
|
||||
PTR_ADDIU a0,a0,UNIT(8)
|
||||
/*
|
||||
* Here we have less then 32(64) bytes to copy. Set up for a loop to
|
||||
* copy one word (or double word) at a time.
|
||||
*/
|
||||
L(ua_chk1w):
|
||||
andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */
|
||||
beq a2,t8,L(ua_smallCopy)
|
||||
PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */
|
||||
PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
|
||||
|
||||
/* copying in words (4-byte or 8-byte chunks) */
|
||||
L(ua_wordCopy_loop):
|
||||
C_LDHI v1,UNIT(0)(a1)
|
||||
C_LDLO v1,UNITM1(1)(a1)
|
||||
PTR_ADDIU a1,a1,UNIT(1)
|
||||
PTR_ADDIU a0,a0,UNIT(1)
|
||||
bne a0,a3,L(ua_wordCopy_loop)
|
||||
C_ST v1,UNIT(-1)(a0)
|
||||
|
||||
/* Copy the last 8 (or 16) bytes */
|
||||
L(ua_smallCopy):
|
||||
beqz a2,L(leave)
|
||||
PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
|
||||
L(ua_smallCopy_loop):
|
||||
lb v1,0(a1)
|
||||
PTR_ADDIU a1,a1,1
|
||||
PTR_ADDIU a0,a0,1
|
||||
bne a0,a3,L(ua_smallCopy_loop)
|
||||
sb v1,-1(a0)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
L(shift):
|
||||
subu a3, zero, a0 # Src and Dest unaligned
|
||||
andi a3, 0x3 # (unoptimized case...)
|
||||
beq a3, zero, L(shft1)
|
||||
subu a2, a3 # a2 = bytes left
|
||||
LWHI t0, 0(a1) # Take care of first odd part
|
||||
LWLO t0, 3(a1)
|
||||
addu a1, a3
|
||||
SWHI t0, 0(a0)
|
||||
addu a0, a3
|
||||
L(shft1):
|
||||
andi t0, a2, 0x3
|
||||
subu a3, a2, t0
|
||||
addu a3, a1
|
||||
L(shfth):
|
||||
LWHI t1, 0(a1) # Limp through, word by word
|
||||
LWLO t1, 3(a1)
|
||||
addiu a0, 4
|
||||
addiu a1, 4
|
||||
bne a1, a3, L(shfth)
|
||||
sw t1, -4(a0)
|
||||
b L(last8) # Handle anything which may be left
|
||||
move a2, t0
|
||||
|
||||
.set at
|
||||
.set reorder
|
||||
END (memcpy)
|
||||
libc_hidden_builtin_def (memcpy)
|
||||
END(MEMCPY_NAME)
|
||||
#ifdef _LIBC
|
||||
libc_hidden_builtin_def (MEMCPY_NAME)
|
||||
#endif
|
||||
|
||||
@ -1,138 +0,0 @@
|
||||
/* Copyright (C) 2002-2012 Free Software Foundation, Inc.
|
||||
This file is part of the GNU C Library.
|
||||
Contributed by Hartvig Ekner <hartvige@mips.com>, 2002.
|
||||
Ported to mips3 n32/n64 by Alexandre Oliva <aoliva@redhat.com>
|
||||
|
||||
The GNU C Library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
The GNU C Library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with the GNU C Library. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include <sysdep.h>
|
||||
#include <sys/asm.h>
|
||||
|
||||
|
||||
/* void *memcpy(void *s1, const void *s2, size_t n);
|
||||
|
||||
This could probably be optimized further. */
|
||||
|
||||
#if __MIPSEB
|
||||
# define LDHI ldl /* high part is left in big-endian */
|
||||
# define SDHI sdl /* high part is left in big-endian */
|
||||
# define LDLO ldr /* low part is right in big-endian */
|
||||
# define SDLO sdr /* low part is right in big-endian */
|
||||
#else
|
||||
# define LDHI ldr /* high part is right in little-endian */
|
||||
# define SDHI sdr /* high part is right in little-endian */
|
||||
# define LDLO ldl /* low part is left in little-endian */
|
||||
# define SDLO sdl /* low part is left in little-endian */
|
||||
#endif
|
||||
|
||||
ENTRY (memcpy)
|
||||
.set noreorder
|
||||
|
||||
slti t0, a2, 16 # Less than 16?
|
||||
bne t0, zero, L(last16)
|
||||
move v0, a0 # Setup exit value before too late
|
||||
|
||||
xor t0, a1, a0 # Find a0/a1 displacement
|
||||
andi t0, 0x7
|
||||
bne t0, zero, L(shift) # Go handle the unaligned case
|
||||
PTR_SUBU t1, zero, a1
|
||||
andi t1, 0x7 # a0/a1 are aligned, but are we
|
||||
beq t1, zero, L(chk8w) # starting in the middle of a word?
|
||||
PTR_SUBU a2, t1
|
||||
LDHI t0, 0(a1) # Yes we are... take care of that
|
||||
PTR_ADDU a1, t1
|
||||
SDHI t0, 0(a0)
|
||||
PTR_ADDU a0, t1
|
||||
|
||||
L(chk8w):
|
||||
andi t0, a2, 0x3f # 64 or more bytes left?
|
||||
beq t0, a2, L(chk1w)
|
||||
PTR_SUBU a3, a2, t0 # Yes
|
||||
PTR_ADDU a3, a1 # a3 = end address of loop
|
||||
move a2, t0 # a2 = what will be left after loop
|
||||
L(lop8w):
|
||||
ld t0, 0(a1) # Loop taking 8 words at a time
|
||||
ld t1, 8(a1)
|
||||
ld t2, 16(a1)
|
||||
ld t3, 24(a1)
|
||||
ld ta0, 32(a1)
|
||||
ld ta1, 40(a1)
|
||||
ld ta2, 48(a1)
|
||||
ld ta3, 56(a1)
|
||||
PTR_ADDIU a0, 64
|
||||
PTR_ADDIU a1, 64
|
||||
sd t0, -64(a0)
|
||||
sd t1, -56(a0)
|
||||
sd t2, -48(a0)
|
||||
sd t3, -40(a0)
|
||||
sd ta0, -32(a0)
|
||||
sd ta1, -24(a0)
|
||||
sd ta2, -16(a0)
|
||||
bne a1, a3, L(lop8w)
|
||||
sd ta3, -8(a0)
|
||||
|
||||
L(chk1w):
|
||||
andi t0, a2, 0x7 # 8 or more bytes left?
|
||||
beq t0, a2, L(last16)
|
||||
PTR_SUBU a3, a2, t0 # Yes, handle them one dword at a time
|
||||
PTR_ADDU a3, a1 # a3 again end address
|
||||
move a2, t0
|
||||
L(lop1w):
|
||||
ld t0, 0(a1)
|
||||
PTR_ADDIU a0, 8
|
||||
PTR_ADDIU a1, 8
|
||||
bne a1, a3, L(lop1w)
|
||||
sd t0, -8(a0)
|
||||
|
||||
L(last16):
|
||||
blez a2, L(lst16e) # Handle last 16 bytes, one at a time
|
||||
PTR_ADDU a3, a2, a1
|
||||
L(lst16l):
|
||||
lb t0, 0(a1)
|
||||
PTR_ADDIU a0, 1
|
||||
PTR_ADDIU a1, 1
|
||||
bne a1, a3, L(lst16l)
|
||||
sb t0, -1(a0)
|
||||
L(lst16e):
|
||||
jr ra # Bye, bye
|
||||
nop
|
||||
|
||||
L(shift):
|
||||
PTR_SUBU a3, zero, a0 # Src and Dest unaligned
|
||||
andi a3, 0x7 # (unoptimized case...)
|
||||
beq a3, zero, L(shft1)
|
||||
PTR_SUBU a2, a3 # a2 = bytes left
|
||||
LDHI t0, 0(a1) # Take care of first odd part
|
||||
LDLO t0, 7(a1)
|
||||
PTR_ADDU a1, a3
|
||||
SDHI t0, 0(a0)
|
||||
PTR_ADDU a0, a3
|
||||
L(shft1):
|
||||
andi t0, a2, 0x7
|
||||
PTR_SUBU a3, a2, t0
|
||||
PTR_ADDU a3, a1
|
||||
L(shfth):
|
||||
LDHI t1, 0(a1) # Limp through, dword by dword
|
||||
LDLO t1, 7(a1)
|
||||
PTR_ADDIU a0, 8
|
||||
PTR_ADDIU a1, 8
|
||||
bne a1, a3, L(shfth)
|
||||
sd t1, -8(a0)
|
||||
b L(last16) # Handle anything which may be left
|
||||
move a2, t0
|
||||
|
||||
.set reorder
|
||||
END (memcpy)
|
||||
libc_hidden_builtin_def (memcpy)
|
||||
Loading…
Reference in New Issue
Block a user