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[powerpc] fe{en,dis}ableexcept optimize bit translations
The exceptions passed to fe{en,dis}ableexcept() are defined in the ABI
as a bitmask, a combination of FE_INVALID, FE_OVERFLOW, etc.
Within the functions, these bits must be translated to/from the corresponding
enable bits in the Floating Point Status Control Register (FPSCR).
This translation is currently done bit-by-bit. The compiler generates
a series of conditional bit operations. Nicely, the "FE" exception
bits are all a uniform offset from the FPSCR enable bits, so the bit-by-bit
operation can instead be performed by a shift with appropriate masking.
This commit is contained in:
Paul A. Clarke
parent
35ffd20dbd
commit
cd7ce12a02
@ -1,3 +1,12 @@
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2019-08-28 Paul A. Clarke <pc@us.ibm.com>
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* sysdeps/powerpc/fpu/fenv_libc.h: Define FPSCR bitmasks.
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(fenv_reg_to_exceptions): Replace bitwise operations with mask-shift.
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(fenv_exceptions_to_reg): New.
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* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Replace bitwise
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operation with call to fenv_exceptions_to_reg().
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* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise.
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2019-08-28 Florian Weimer <fweimer@redhat.com>
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* misc/mntent.c (struct mntent_buffer): Define.
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@ -33,16 +33,7 @@ fedisableexcept (int excepts)
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excepts = (excepts | FE_INVALID) & ~ FE_ALL_INVALID;
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/* Sets the new exception mask. */
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if (excepts & FE_INEXACT)
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fe.l &= ~(1 << (31 - FPSCR_XE));
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if (excepts & FE_DIVBYZERO)
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fe.l &= ~(1 << (31 - FPSCR_ZE));
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if (excepts & FE_UNDERFLOW)
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fe.l &= ~(1 << (31 - FPSCR_UE));
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if (excepts & FE_OVERFLOW)
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fe.l &= ~(1 << (31 - FPSCR_OE));
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if (excepts & FE_INVALID)
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fe.l &= ~(1 << (31 - FPSCR_VE));
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fe.l &= ~ fenv_exceptions_to_reg (excepts);
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if (fe.l != curr.l)
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fesetenv_register (fe.fenv);
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@ -33,16 +33,7 @@ feenableexcept (int excepts)
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excepts = (excepts | FE_INVALID) & ~ FE_ALL_INVALID;
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/* Sets the new exception mask. */
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if (excepts & FE_INEXACT)
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fe.l |= (1 << (31 - FPSCR_XE));
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if (excepts & FE_DIVBYZERO)
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fe.l |= (1 << (31 - FPSCR_ZE));
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if (excepts & FE_UNDERFLOW)
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fe.l |= (1 << (31 - FPSCR_UE));
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if (excepts & FE_OVERFLOW)
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fe.l |= (1 << (31 - FPSCR_OE));
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if (excepts & FE_INVALID)
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fe.l |= (1 << (31 - FPSCR_VE));
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fe.l |= fenv_exceptions_to_reg (excepts);
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if (fe.l != curr.l)
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fesetenv_register (fe.fenv);
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@ -128,60 +128,108 @@ __fesetround_inline_nocheck (const int round)
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asm volatile ("mtfsfi 7,%0" : : "i" (round));
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}
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#define FPSCR_MASK(bit) (1 << (31 - (bit)))
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/* Definitions of all the FPSCR bit numbers */
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enum {
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FPSCR_FX = 0, /* exception summary */
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#define FPSCR_FX_MASK (FPSCR_MASK (FPSCR_FX))
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FPSCR_FEX, /* enabled exception summary */
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#define FPSCR_FEX_MASK (FPSCR_MASK FPSCR_FEX))
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FPSCR_VX, /* invalid operation summary */
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#define FPSCR_VX_MASK (FPSCR_MASK (FPSCR_VX))
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FPSCR_OX, /* overflow */
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#define FPSCR_OX_MASK (FPSCR_MASK (FPSCR_OX))
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FPSCR_UX, /* underflow */
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#define FPSCR_UX_MASK (FPSCR_MASK (FPSCR_UX))
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FPSCR_ZX, /* zero divide */
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#define FPSCR_ZX_MASK (FPSCR_MASK (FPSCR_ZX))
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FPSCR_XX, /* inexact */
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#define FPSCR_XX_MASK (FPSCR_MASK (FPSCR_XX))
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FPSCR_VXSNAN, /* invalid operation for sNaN */
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#define FPSCR_VXSNAN_MASK (FPSCR_MASK (FPSCR_VXSNAN))
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FPSCR_VXISI, /* invalid operation for Inf-Inf */
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#define FPSCR_VXISI_MASK (FPSCR_MASK (FPSCR_VXISI))
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FPSCR_VXIDI, /* invalid operation for Inf/Inf */
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#define FPSCR_VXIDI_MASK (FPSCR_MASK (FPSCR_VXIDI))
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FPSCR_VXZDZ, /* invalid operation for 0/0 */
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#define FPSCR_VXZDZ_MASK (FPSCR_MASK (FPSCR_VXZDZ))
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FPSCR_VXIMZ, /* invalid operation for Inf*0 */
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#define FPSCR_VXIMZ_MASK (FPSCR_MASK (FPSCR_VXIMZ))
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FPSCR_VXVC, /* invalid operation for invalid compare */
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#define FPSCR_VXVC_MASK (FPSCR_MASK (FPSCR_VXVC))
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FPSCR_FR, /* fraction rounded [fraction was incremented by round] */
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#define FPSCR_FR_MASK (FPSCR_MASK (FPSCR_FR))
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FPSCR_FI, /* fraction inexact */
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#define FPSCR_FI_MASK (FPSCR_MASK (FPSCR_FI))
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FPSCR_FPRF_C, /* result class descriptor */
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#define FPSCR_FPRF_C_MASK (FPSCR_MASK (FPSCR_FPRF_C))
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FPSCR_FPRF_FL, /* result less than (usually, less than 0) */
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#define FPSCR_FPRF_FL_MASK (FPSCR_MASK (FPSCR_FPRF_FL))
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FPSCR_FPRF_FG, /* result greater than */
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#define FPSCR_FPRF_FG_MASK (FPSCR_MASK (FPSCR_FPRF_FG))
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FPSCR_FPRF_FE, /* result equal to */
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#define FPSCR_FPRF_FE_MASK (FPSCR_MASK (FPSCR_FPRF_FE))
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FPSCR_FPRF_FU, /* result unordered */
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#define FPSCR_FPRF_FU_MASK (FPSCR_MASK (FPSCR_FPRF_FU))
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FPSCR_20, /* reserved */
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FPSCR_VXSOFT, /* invalid operation set by software */
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#define FPSCR_VXSOFT_MASK (FPSCR_MASK (FPSCR_VXSOFT))
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FPSCR_VXSQRT, /* invalid operation for square root */
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#define FPSCR_VXSQRT_MASK (FPSCR_MASK (FPSCR_VXSQRT))
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FPSCR_VXCVI, /* invalid operation for invalid integer convert */
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#define FPSCR_VXCVI_MASK (FPSCR_MASK (FPSCR_VXCVI))
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FPSCR_VE, /* invalid operation exception enable */
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#define FPSCR_VE_MASK (FPSCR_MASK (FPSCR_VE))
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FPSCR_OE, /* overflow exception enable */
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#define FPSCR_OE_MASK (FPSCR_MASK (FPSCR_OE))
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FPSCR_UE, /* underflow exception enable */
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#define FPSCR_UE_MASK (FPSCR_MASK (FPSCR_UE))
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FPSCR_ZE, /* zero divide exception enable */
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#define FPSCR_ZE_MASK (FPSCR_MASK (FPSCR_ZE))
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FPSCR_XE, /* inexact exception enable */
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#define FPSCR_XE_MASK (FPSCR_MASK (FPSCR_XE))
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#ifdef _ARCH_PWR6
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FPSCR_29, /* Reserved in ISA 2.05 */
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#define FPSCR_NI_MASK (FPSCR_MASK (FPSCR_29))
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#else
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FPSCR_NI /* non-IEEE mode (typically, no denormalised numbers) */
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FPSCR_NI, /* non-IEEE mode (typically, no denormalised numbers) */
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#define FPSCR_NI_MASK (FPSCR_MASK (FPSCR_NI))
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#endif /* _ARCH_PWR6 */
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/* the remaining two least-significant bits keep the rounding mode */
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FPSCR_RN_hi,
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#define FPSCR_RN_hi_MASK (FPSCR_MASK (FPSCR_RN_hi))
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FPSCR_RN_lo
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#define FPSCR_RN_lo_MASK (FPSCR_MASK (FPSCR_RN_lo))
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};
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#define FPSCR_RN_MASK (FPSCR_RN_hi_MASK|FPSCR_RN_lo_MASK)
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#define FPSCR_ENABLES_MASK \
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(FPSCR_VE_MASK|FPSCR_OE_MASK|FPSCR_UE_MASK|FPSCR_ZE_MASK|FPSCR_XE_MASK)
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#define FPSCR_BASIC_EXCEPTIONS_MASK \
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(FPSCR_VX_MASK|FPSCR_OX_MASK|FPSCR_UX_MASK|FPSCR_ZX_MASK|FPSCR_XX_MASK)
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#define FPSCR_CONTROL_MASK (FPSCR_ENABLES_MASK|FPSCR_NI_MASK|FPSCR_RN_MASK)
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/* The bits in the FENV(1) ABI for exceptions correspond one-to-one with bits
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in the FPSCR, albeit shifted to different but corresponding locations.
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Similarly, the exception indicator bits in the FPSCR correspond one-to-one
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with the exception enable bits. It is thus possible to map the FENV(1)
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exceptions directly to the FPSCR enables with a simple mask and shift,
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and vice versa. */
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#define FPSCR_EXCEPT_TO_ENABLE_SHIFT 22
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static inline int
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fenv_reg_to_exceptions (unsigned long long l)
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{
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int result = 0;
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if (l & (1 << (31 - FPSCR_XE)))
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result |= FE_INEXACT;
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if (l & (1 << (31 - FPSCR_ZE)))
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result |= FE_DIVBYZERO;
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if (l & (1 << (31 - FPSCR_UE)))
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result |= FE_UNDERFLOW;
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if (l & (1 << (31 - FPSCR_OE)))
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result |= FE_OVERFLOW;
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if (l & (1 << (31 - FPSCR_VE)))
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result |= FE_INVALID;
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return result;
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return (((int)l) & FPSCR_ENABLES_MASK) << FPSCR_EXCEPT_TO_ENABLE_SHIFT;
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}
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static inline unsigned long long
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fenv_exceptions_to_reg (int excepts)
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{
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return (unsigned long long)
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(excepts & FE_ALL_EXCEPT) >> FPSCR_EXCEPT_TO_ENABLE_SHIFT;
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}
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#ifdef _ARCH_PWR6
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