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aarch64: MTE compatible strlen
Introduce an Arm MTE compatible strlen implementation. The existing implementation assumes that any access to the pages in which the string resides is safe. This assumption is not true when MTE is enabled. This patch updates the algorithm to ensure that accesses remain within the bounds of an MTE tag (16-byte chunks) and improves overall performance on modern cores. On cores with less efficient Advanced SIMD implementation such as Cortex-A53 it can be slower. Benchmarked on Cortex-A72, Cortex-A53, Neoverse N1. Co-authored-by: Wilco Dijkstra <wilco.dijkstra@arm.com>
This commit is contained in:
Andrea Corallo
Szabolcs Nagy
parent
49beaaec1b
commit
a365ac45b7
@ -20,205 +20,78 @@
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/* Assumptions:
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*
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* ARMv8-a, AArch64, unaligned accesses, min page size 4k.
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* ARMv8-a, AArch64, Advanced SIMD.
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* MTE compatible.
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*/
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#ifndef STRLEN
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# define STRLEN __strlen
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#endif
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/* To test the page crossing code path more thoroughly, compile with
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-DTEST_PAGE_CROSS - this will force all calls through the slower
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entry path. This option is not intended for production use. */
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/* Arguments and results. */
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#define srcin x0
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#define len x0
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#define result x0
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/* Locals and temporaries. */
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#define src x1
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#define data1 x2
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#define data2 x3
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#define has_nul1 x4
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#define has_nul2 x5
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#define tmp1 x4
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#define tmp2 x5
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#define tmp3 x6
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#define tmp4 x7
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#define zeroones x8
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#define synd x2
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#define tmp x3
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#define wtmp w3
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#define shift x4
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/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
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(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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can be done in parallel across the entire word. A faster check
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(X - 1) & 0x80 is zero for non-NUL ASCII characters, but gives
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false hits for characters 129..255. */
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#define data q0
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#define vdata v0
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#define vhas_nul v1
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#define vrepmask v2
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#define vend v3
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#define dend d3
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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#define REP8_80 0x8080808080808080
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/* Core algorithm:
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#ifdef TEST_PAGE_CROSS
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# define MIN_PAGE_SIZE 16
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#else
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# define MIN_PAGE_SIZE 4096
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#endif
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For each 16-byte chunk we calculate a 64-bit syndrome value with four bits
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per byte. For even bytes, bits 0-3 are set if the relevant byte matched the
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requested character or the byte is NUL. Bits 4-7 must be zero. Bits 4-7 are
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set likewise for odd bytes so that adjacent bytes can be merged. Since the
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bits in the syndrome reflect the order in which things occur in the original
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string, counting trailing zeros identifies exactly which byte matched. */
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/* Since strings are short on average, we check the first 16 bytes
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of the string for a NUL character. In order to do an unaligned ldp
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safely we have to do a page cross check first. If there is a NUL
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byte we calculate the length from the 2 8-byte words using
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conditional select to reduce branch mispredictions (it is unlikely
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strlen will be repeatedly called on strings with the same length).
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If the string is longer than 16 bytes, we align src so don't need
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further page cross checks, and process 32 bytes per iteration
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using the fast NUL check. If we encounter non-ASCII characters,
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fallback to a second loop using the full NUL check.
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If the page cross check fails, we read 16 bytes from an aligned
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address, remove any characters before the string, and continue
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in the main loop using aligned loads. Since strings crossing a
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page in the first 16 bytes are rare (probability of
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16/MIN_PAGE_SIZE ~= 0.4%), this case does not need to be optimized.
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AArch64 systems have a minimum page size of 4k. We don't bother
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checking for larger page sizes - the cost of setting up the correct
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page size is just not worth the extra gain from a small reduction in
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the cases taking the slow path. Note that we only care about
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whether the first fetch, which may be misaligned, crosses a page
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boundary. */
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ENTRY_ALIGN (STRLEN, 6)
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ENTRY (STRLEN)
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DELOUSE (0)
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DELOUSE (1)
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and tmp1, srcin, MIN_PAGE_SIZE - 1
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mov zeroones, REP8_01
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cmp tmp1, MIN_PAGE_SIZE - 16
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b.gt L(page_cross)
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ldp data1, data2, [srcin]
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#ifdef __AARCH64EB__
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/* For big-endian, carry propagation (if the final byte in the
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string is 0x01) means we cannot use has_nul1/2 directly.
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Since we expect strings to be small and early-exit,
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byte-swap the data now so has_null1/2 will be correct. */
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rev data1, data1
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rev data2, data2
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#endif
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sub tmp1, data1, zeroones
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orr tmp2, data1, REP8_7f
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sub tmp3, data2, zeroones
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orr tmp4, data2, REP8_7f
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bics has_nul1, tmp1, tmp2
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bic has_nul2, tmp3, tmp4
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ccmp has_nul2, 0, 0, eq
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beq L(main_loop_entry)
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bic src, srcin, 15
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mov wtmp, 0xf00f
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ld1 {vdata.16b}, [src]
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dup vrepmask.8h, wtmp
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cmeq vhas_nul.16b, vdata.16b, 0
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lsl shift, srcin, 2
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and vhas_nul.16b, vhas_nul.16b, vrepmask.16b
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addp vend.16b, vhas_nul.16b, vhas_nul.16b /* 128->64 */
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fmov synd, dend
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lsr synd, synd, shift
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cbz synd, L(loop)
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/* Enter with C = has_nul1 == 0. */
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csel has_nul1, has_nul1, has_nul2, cc
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mov len, 8
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rev has_nul1, has_nul1
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clz tmp1, has_nul1
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csel len, xzr, len, cc
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add len, len, tmp1, lsr 3
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rbit synd, synd
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clz result, synd
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lsr result, result, 2
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ret
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/* The inner loop processes 32 bytes per iteration and uses the fast
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NUL check. If we encounter non-ASCII characters, use a second
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loop with the accurate NUL check. */
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.p2align 4
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L(main_loop_entry):
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bic src, srcin, 15
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sub src, src, 16
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L(main_loop):
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ldp data1, data2, [src, 32]!
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L(page_cross_entry):
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sub tmp1, data1, zeroones
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sub tmp3, data2, zeroones
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orr tmp2, tmp1, tmp3
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tst tmp2, zeroones, lsl 7
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bne 1f
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ldp data1, data2, [src, 16]
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sub tmp1, data1, zeroones
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sub tmp3, data2, zeroones
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orr tmp2, tmp1, tmp3
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tst tmp2, zeroones, lsl 7
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beq L(main_loop)
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add src, src, 16
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1:
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/* The fast check failed, so do the slower, accurate NUL check. */
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orr tmp2, data1, REP8_7f
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orr tmp4, data2, REP8_7f
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bics has_nul1, tmp1, tmp2
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bic has_nul2, tmp3, tmp4
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ccmp has_nul2, 0, 0, eq
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beq L(nonascii_loop)
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.p2align 5
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L(loop):
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ldr data, [src, 16]!
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cmeq vhas_nul.16b, vdata.16b, 0
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umaxp vend.16b, vhas_nul.16b, vhas_nul.16b
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fmov synd, dend
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cbz synd, L(loop)
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/* Enter with C = has_nul1 == 0. */
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L(tail):
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#ifdef __AARCH64EB__
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/* For big-endian, carry propagation (if the final byte in the
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string is 0x01) means we cannot use has_nul1/2 directly. The
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easiest way to get the correct byte is to byte-swap the data
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and calculate the syndrome a second time. */
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csel data1, data1, data2, cc
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rev data1, data1
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sub tmp1, data1, zeroones
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orr tmp2, data1, REP8_7f
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bic has_nul1, tmp1, tmp2
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#else
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csel has_nul1, has_nul1, has_nul2, cc
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and vhas_nul.16b, vhas_nul.16b, vrepmask.16b
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addp vend.16b, vhas_nul.16b, vhas_nul.16b /* 128->64 */
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sub result, src, srcin
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fmov synd, dend
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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sub len, src, srcin
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rev has_nul1, has_nul1
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add tmp2, len, 8
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clz tmp1, has_nul1
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csel len, len, tmp2, cc
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add len, len, tmp1, lsr 3
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clz tmp, synd
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add result, result, tmp, lsr 2
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ret
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L(nonascii_loop):
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ldp data1, data2, [src, 16]!
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sub tmp1, data1, zeroones
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orr tmp2, data1, REP8_7f
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sub tmp3, data2, zeroones
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orr tmp4, data2, REP8_7f
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bics has_nul1, tmp1, tmp2
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bic has_nul2, tmp3, tmp4
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ccmp has_nul2, 0, 0, eq
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bne L(tail)
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ldp data1, data2, [src, 16]!
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sub tmp1, data1, zeroones
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orr tmp2, data1, REP8_7f
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sub tmp3, data2, zeroones
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orr tmp4, data2, REP8_7f
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bics has_nul1, tmp1, tmp2
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bic has_nul2, tmp3, tmp4
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ccmp has_nul2, 0, 0, eq
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beq L(nonascii_loop)
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b L(tail)
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/* Load 16 bytes from [srcin & ~15] and force the bytes that precede
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srcin to 0x7f, so we ignore any NUL bytes before the string.
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Then continue in the aligned loop. */
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L(page_cross):
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bic src, srcin, 15
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ldp data1, data2, [src]
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lsl tmp1, srcin, 3
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mov tmp4, -1
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#ifdef __AARCH64EB__
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/* Big-endian. Early bytes are at MSB. */
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lsr tmp1, tmp4, tmp1 /* Shift (tmp1 & 63). */
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#else
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/* Little-endian. Early bytes are at LSB. */
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lsl tmp1, tmp4, tmp1 /* Shift (tmp1 & 63). */
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#endif
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orr tmp1, tmp1, REP8_80
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orn data1, data1, tmp1
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orn tmp2, data2, tmp1
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tst srcin, 8
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csel data1, data1, tmp4, eq
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csel data2, data2, tmp2, eq
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b L(page_cross_entry)
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END (STRLEN)
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weak_alias (STRLEN, strlen)
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libc_hidden_builtin_def (strlen)
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