mirror/glibc
2
0
Fork 0
mirror of git://sourceware.org/git/glibc.git synced 2025-01-30 12:31:53 +08:00
Code Issues Packages Projects Releases Wiki Activity

Support non-inclusive caches on Intel processors

Browse Source 
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support
	non-inclusive caches on Intel processors.
This commit is contained in:
H.J. Lu 2016-05-13 07:18:25 -07:00
parent 4cf6c72fd2
commit 9e4ec3e816
2 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
ChangeLog
View File

@ -1,3 +1,8 @@
2016-05-13 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support
non-inclusive caches on Intel processors.
2016-05-13 Florian Weimer <fweimer@redhat.com>
* malloc/malloc.c (dumped_main_arena_start)

12
sysdeps/x86/cacheinfo.c
View File

@ -492,6 +492,9 @@ init_cacheinfo (void)
{
data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
bool inclusive_cache = true;
/* Try L3 first. */
level = 3;
shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
@ -500,7 +503,7 @@ init_cacheinfo (void)
{
/* Try L2 otherwise. */
level = 2;
shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
shared = core;
}
/* Figure out the number of logical threads that share the
@ -526,6 +529,9 @@ init_cacheinfo (void)
}
while (((eax >> 5) & 0x7) != level);
/* Check if cache is inclusive of lower cache levels. */
inclusive_cache = (edx & 0x2) != 0;
threads = (eax >> 14) & 0x3ff;
/* If max_cpuid >= 11, THREADS is the maximum number of
@ -592,6 +598,10 @@ init_cacheinfo (void)
threads. */
if (shared > 0 && threads > 0)
shared /= threads;
/* Account for non-inclusive L2 and L3 caches. */
if (level == 3 && !inclusive_cache)
shared += core;
}
/* This spells out "AuthenticAMD". */
else if (is_amd)