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This patch adds detection of availability for AVX512F and AVX512DQ ISAs.
* sysdeps/x86_64/multiarch/init-arch.h (bit_AVX512F_Usable, bit_AVX512DQ_Usable, bit_Opmask_state, bit_ZMM0_15_state, bit_ZMM16_31_state): New macro. * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): Check and set bit_AVX512F_Usable, bit_AVX512DQ_Usable.
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@ -1,3 +1,11 @@
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2015-06-08 Andrew Senkevich <andrew.senkevich@intel.com>
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* sysdeps/x86_64/multiarch/init-arch.h (bit_AVX512F_Usable,
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bit_AVX512DQ_Usable, bit_Opmask_state, bit_ZMM0_15_state,
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bit_ZMM16_31_state): New macro.
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* sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
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Check and set bit_AVX512F_Usable, bit_AVX512DQ_Usable.
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2015-06-08 Joseph Myers <joseph@codesourcery.com>
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* include/stdio.h (__open_memstream): Say "C++ tests" in comment.
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@ -179,6 +179,23 @@ __init_cpu_features (void)
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if (CPUID_AVX2)
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__cpu_features.feature[index_AVX2_Usable]
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|= bit_AVX2_Usable | bit_AVX_Fast_Unaligned_Load;
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/* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
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ZMM16-ZMM31 state are enabled. */
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if ((xcrlow & (bit_Opmask_state | bit_ZMM0_15_state
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| bit_ZMM16_31_state)) ==
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(bit_Opmask_state | bit_ZMM0_15_state | bit_ZMM16_31_state))
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{
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/* Determine if AVX512F is usable. */
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if (CPUID_AVX512F)
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{
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__cpu_features.feature[index_AVX512F_Usable]
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|= bit_AVX512F_Usable;
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/* Determine if AVX512DQ is usable. */
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if (CPUID_AVX512DQ)
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__cpu_features.feature[index_AVX512DQ_Usable]
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|= bit_AVX512DQ_Usable;
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}
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}
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/* Determine if FMA is usable. */
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if (CPUID_FMA)
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__cpu_features.feature[index_FMA_Usable] |= bit_FMA_Usable;
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@ -26,6 +26,8 @@
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#define bit_Slow_SSE4_2 (1 << 9)
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#define bit_AVX2_Usable (1 << 10)
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#define bit_AVX_Fast_Unaligned_Load (1 << 11)
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#define bit_AVX512F_Usable (1 << 12)
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#define bit_AVX512DQ_Usable (1 << 13)
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/* CPUID Feature flags. */
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@ -43,10 +45,15 @@
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/* COMMON_CPUID_INDEX_7. */
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#define bit_RTM (1 << 11)
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#define bit_AVX2 (1 << 5)
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#define bit_AVX512F (1 << 16)
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#define bit_AVX512DQ (1 << 17)
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/* XCR0 Feature flags. */
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#define bit_XMM_state (1 << 1)
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#define bit_YMM_state (2 << 1)
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#define bit_Opmask_state (1 << 5)
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#define bit_ZMM0_15_state (1 << 6)
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#define bit_ZMM16_31_state (1 << 7)
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/* The integer bit array index for the first set of internal feature bits. */
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# define FEATURE_INDEX_1 0
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@ -76,6 +83,8 @@
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# define index_Slow_SSE4_2 FEATURE_INDEX_1*FEATURE_SIZE
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# define index_AVX2_Usable FEATURE_INDEX_1*FEATURE_SIZE
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# define index_AVX_Fast_Unaligned_Load FEATURE_INDEX_1*FEATURE_SIZE
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# define index_AVX512F_Usable FEATURE_INDEX_1*FEATURE_SIZE
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# define index_AVX512DQ_Usable FEATURE_INDEX_1*FEATURE_SIZE
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#else /* __ASSEMBLER__ */
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@ -152,6 +161,10 @@ extern const struct cpu_features *__get_cpu_features (void)
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HAS_CPUID_FLAG (COMMON_CPUID_INDEX_7, ebx, bit_RTM)
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# define CPUID_AVX2 \
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HAS_CPUID_FLAG (COMMON_CPUID_INDEX_7, ebx, bit_AVX2)
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# define CPUID_AVX512F \
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HAS_CPUID_FLAG (COMMON_CPUID_INDEX_7, ebx, bit_AVX512F)
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# define CPUID_AVX512DQ \
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HAS_CPUID_FLAG (COMMON_CPUID_INDEX_7, ebx, bit_AVX512DQ)
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/* HAS_* evaluates to true if we may use the feature at runtime. */
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# define HAS_SSE2 HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, edx, bit_SSE2)
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@ -172,6 +185,8 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define index_Slow_SSE4_2 FEATURE_INDEX_1
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# define index_AVX2_Usable FEATURE_INDEX_1
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# define index_AVX_Fast_Unaligned_Load FEATURE_INDEX_1
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# define index_AVX512F_Usable FEATURE_INDEX_1
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# define index_AVX512DQ_Usable FEATURE_INDEX_1
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# define HAS_ARCH_FEATURE(name) \
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((__get_cpu_features ()->feature[index_##name] & (bit_##name)) != 0)
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@ -182,6 +197,8 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define HAS_FAST_UNALIGNED_LOAD HAS_ARCH_FEATURE (Fast_Unaligned_Load)
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# define HAS_AVX HAS_ARCH_FEATURE (AVX_Usable)
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# define HAS_AVX2 HAS_ARCH_FEATURE (AVX2_Usable)
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# define HAS_AVX512F HAS_ARCH_FEATURE (AVX512F_Usable)
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# define HAS_AVX512DQ HAS_ARCH_FEATURE (AVX512DQ_Usable)
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# define HAS_FMA HAS_ARCH_FEATURE (FMA_Usable)
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# define HAS_FMA4 HAS_ARCH_FEATURE (FMA4_Usable)
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# define HAS_AVX_FAST_UNALIGNED_LOAD HAS_ARCH_FEATURE (AVX_Fast_Unaligned_Load)
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