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AArch64: Simplify lrint

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Simplify lrint.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
This commit is contained in:
Wilco Dijkstra 2025-01-02 19:46:07 +00:00
parent 0a021727bc
commit 4c11379106
1 changed files with 0 additions and 51 deletions
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51
sysdeps/aarch64/fpu/s_lrint.c
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@ -22,60 +22,9 @@
#include <math-barriers.h>
#include <libm-alias-double.h>
# define IREG_SIZE 64
# ifdef __ILP32__
# define OREG_SIZE 32
# else
# define OREG_SIZE 64
# endif
# define IREGS "d"
#if OREG_SIZE == 32
# define OREGS "w"
#else
# define OREGS "x"
#endif
long int
__lrint (double x)
{
#if IREG_SIZE == 64 && OREG_SIZE == 32
long int result;
if (__builtin_fabs (x) > INT32_MAX)
{
/* Converting large values to a 32 bit int may cause the frintx/fcvtza
sequence to set both FE_INVALID and FE_INEXACT. To avoid this
check the rounding mode and do a single instruction with the
appropriate rounding mode. */
switch (get_rounding_mode ())
{
case FE_TONEAREST:
asm volatile ("fcvtns" "\t%" OREGS "0, %" IREGS "1"
: "=r" (result) : "w" (x));
break;
case FE_UPWARD:
asm volatile ("fcvtps" "\t%" OREGS "0, %" IREGS "1"
: "=r" (result) : "w" (x));
break;
case FE_DOWNWARD:
asm volatile ("fcvtms" "\t%" OREGS "0, %" IREGS "1"
: "=r" (result) : "w" (x));
break;
case FE_TOWARDZERO:
default:
asm volatile ("fcvtzs" "\t%" OREGS "0, %" IREGS "1"
: "=r" (result) : "w" (x));
}
return result;
}
#endif
double r = __builtin_rint (x);
/* Prevent gcc from calling lrint directly when compiled with