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[powerpc] fegetenv_status: simplify instruction generation
fegetenv_status() wants to use the lighter weight instruction 'mffsl' for reading the Floating-Point Status and Control Register (FPSCR). It currently will use it directly if compiled '-mcpu=power9', and will perform a runtime check (cpu_supports("arch_3_00")) otherwise. Nicely, it turns out that the 'mffsl' instruction will decode to 'mffs' on architectures older than "arch_3_00" because the additional bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset of 'mffsl'. So, just generate 'mffsl'.
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@ -1,3 +1,8 @@
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2019-08-28 Paul A. Clarke <pc@us.ibm.com>
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* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status_ISA300): Delete.
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(fegetenv_status): Generate 'mffsl' unconditionally.
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2019-08-28 Paul A. Clarke <pc@us.ibm.com>
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* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Utilize lightweight
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@ -35,9 +35,12 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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#define fegetenv_register() __builtin_mffs()
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/* Equivalent to fegetenv_register, but only returns bits for
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status, exception enables, and mode. */
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#define fegetenv_status_ISA300() \
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status, exception enables, and mode.
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Nicely, it turns out that the 'mffsl' instruction will decode to
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'mffs' on architectures older than "power9" because the additional
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bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset
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of 'mffsl'. */
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#define fegetenv_status() \
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({register double __fr; \
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__asm__ __volatile__ ( \
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".machine push; .machine \"power9\"; mffsl %0; .machine pop" \
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@ -45,18 +48,6 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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__fr; \
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})
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#ifdef _ARCH_PWR9
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# define fegetenv_status() fegetenv_status_ISA300()
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#elif defined __BUILTIN_CPU_SUPPORTS__
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# define fegetenv_status() \
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(__glibc_likely (__builtin_cpu_supports ("arch_3_00")) \
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? fegetenv_status_ISA300() \
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: fegetenv_register() \
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)
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#else
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# define fegetenv_status() fegetenv_register ()
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#endif
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/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */
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#define fesetenv_register(env) \
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do { \
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