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fa18217f60
This patch would like to remove the unnecessary option for the vector SAT_ADD testcases at first. And the different optimization option like O2 and O3 will be passed to the test files for rtl expand dump check. If there are different dump check times for different optimization options, the target no-opts and/or any-opts will be leveraged for the dg-final check. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Remove the unnecessary option and refine the rtl IFN dump check. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com> |
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