Jia-Wei Chen a62d957342 RISC-V: Optimize RVV epilogue logic.
Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction
"addi sp,sp,0". Add checking segement to skip that case.

This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_epilogue):
	Do not emit useless add sp, sp, 0 instrutions.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
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This directory contains the GNU Compiler Collection (GCC).

The GNU Compiler Collection is free software.  See the files whose
names start with COPYING for copying permission.  The manuals, and
some of the runtime libraries, are under different terms; see the
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The directory INSTALL contains copies of the installation information
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See the file gcc/doc/gcc.texi (together with other files that it
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