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If an insn requires two operands to be tied, and the input operand dies in the insn, IRA acts as though there were a copy from the input to the output with the same execution frequency as the insn. Allocating the same register to the input and the output then saves the cost of a move. If there is no such tie, but an input operand nevertheless dies in the insn, IRA creates a similar move, but with an eighth of the frequency. This helps to ensure that chains of instructions reuse registers in a natural way, rather than using arbitrarily different registers for no reason. This heuristic seems to work well in the vast majority of cases. However, for SVE, the handling of untied operands ends up creating copies between dying predicate registers and vector outputs, even though vector and predicate registers are distinct classes and can never be tied. This is a particular problem because the dying predicate tends to be the loop control predicate, which is used by most instructions in a vector loop and so (rightly) has a very high allocation priority. Any copies involving the loop predicate therefore tend to get processed before copies involving only vector registers. The end result is that we tend to allocate the output of the last vector instruction in a loop ahead of its natural place in the allocation order and don't benefit from chains created between vector registers. This patch tries to avoid the problem by not adding register shuffle copies if there appears to be no chance that the two operands could be allocated to the same register. 2019-09-21 Richard Sandiford <richard.sandiford@arm.com> gcc/ * ira-conflicts.c (can_use_same_reg_p): New function. (process_reg_shuffles): Take an insn parameter. Ignore cases in which input operand op_num could seemingly never be allocated to the same register as the destination. (add_insn_allocno_copies): Update call to process_reg_shuffles. gcc/testsuite/ * gcc.target/aarch64/sve/cond_convert_1.c: Remove XFAILs. * gcc.target/aarch64/sve/cond_convert_4.c: Likewise. * gcc.target/aarch64/sve/cond_unary_2.c: Likewise. From-SVN: r276018
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