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The DCache clean & ICache invalidation requirements for instructions to be data coherence are discoverable through new fields in CTR_EL0. Let's support the two bits if they are enabled, the CPU core will not execute the unnecessary DCache clean or Icache Invalidation instructions. 2019-09-25 Shaokun Zhang <zhangshaokun@hisilicon.com> * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Add support for CTR_EL0.IDC and CTR_EL0.DIC. From-SVN: r276122
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