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Besides changing the set of registers that needs to be cleared inline, this patch also generates the push and pop to save and restore callee-saved registers without trusting the callee inline. To make the code more future-proof, this (currently) Armv8.1-M specific behavior is expressed in terms of clearing of callee-saved registers rather than directly based on the targets. The patch contains 1 subtlety: Debug information is disabled for push and pop because the REG_CFA_RESTORE notes used to describe popping of registers do not stack. Instead, they just reset the debug state for the register to the one at the beginning of the function, which is incorrect for a register that is pushed twice (in prologue and before nonsecure call) and then popped for the first time. In particular, this occasionally trips CFI note creation code when there are two codepaths to the epilogue, one of which does not go through the nonsecure call. Obviously this mean that debugging between the push and pop is not reliable. *** gcc/ChangeLog *** 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early. (cmse_nonsecure_call_clear_caller_saved): Rename into ... (cmse_nonsecure_call_inline_register_clear): This. Save and clear callee-saved GPRs as well as clear ip register before doing a nonsecure call then restore callee-saved GPRs after it when targeting Armv8.1-M Mainline. (arm_reorg): Adapt to function rename. *** gcc/testsuite/ChangeLog *** 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse-1.c: Add check for PUSH and POP and update CLRM check. * gcc.target/arm/cmse/cmse-14.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft-sp/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft-sp/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/union-1.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/union-2.c: Likewise.
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