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aarch64 needs to skip memory address validation for LD1R insns. Skipping the address validation may result in LRA crash for some targets when usual memory constraint is used. This patch introduces define_relaxed_memory_constraint, skipping address validation for it, and defining relaxed memory for aarch64 LD1r insn memory operand. gcc/ChangeLog: PR target/99581 * config/aarch64/constraints.md (UtQ): Use define_relaxed_memory_constraint for it. * doc/md.texi (define_relaxed_memory_constraint): Describe it. * genoutput.c (main): Process DEFINE_RELAXED_MEMORY_CONSTRAINT. * genpreds.c (constraint_data): Add bitfield is_relaxed_memory. (have_relaxed_memory_constraints): New static var. (relaxed_memory_start, relaxed_memory_end): Ditto. (add_constraint): Add arg is_relaxed_memory. Check name for relaxed memory. Set up is_relaxed_memory in constraint_data and have_relaxed_memory_constraints. Adjust calls. (choose_enum_order): Process relaxed memory. (write_tm_preds_h): Ditto. (main): Process DEFINE_RELAXED_MEMORY_CONSTRAINT. * gensupport.c (process_rtx): Process DEFINE_RELAXED_MEMORY_CONSTRAINT. * ira-costs.c (record_reg_classes): Process CT_RELAXED_MEMORY. * ira-lives.c (single_reg_class): Use insn_extra_relaxed_memory_constraint. * ira.c (ira_setup_alts): CT_RELAXED_MEMORY. * lra-constraints.c (valid_address_p): Use insn_extra_relaxed_memory_constraint instead of other memory constraints. (process_alt_operands): Process CT_RELAXED_MEMORY. (curr_insn_transform): Use insn_extra_relaxed_memory_constraint. * recog.c (asm_operand_ok, preprocess_constraints): Process CT_RELAXED_MEMORY. * reload.c (find_reloads): Ditto. * rtl.def (DEFINE_RELAXED_MEMORY_CONSTRAINT): New. * stmt.c (parse_input_constraint): Use insn_extra_relaxed_memory_constraint. gcc/testsuite/ChangeLog: PR target/99581 * gcc.target/powerpc/pr99581.c: New.
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