* gcc-interface/decl.c (components_to_record): Do not reorder fields
in packed record types if they contain fixed-size fields that cannot
be laid out in a packed manner.
From-SVN: r276036
Remove dead code for the the TARGET_LINK_STACK which is not
applicable to Darwin. Use MACHOPIC_PURE instead of a hard-wired
PIC level to determine the stub kind.
Merge common code blocks.
gcc/ChangeLog:
2019-09-22 Iain Sandoe <iain@sandoe.co.uk>
* config/rs6000/rs6000.c (machopic_output_stub): Remove dead
code. Merge code blocks with common conditionals. Use declared
macro instead of a magic number for PIC level.
From-SVN: r276030
PR middle-end/91830 - Bogus -Warray-bounds on strcpy into a member
of a subobject compiling binutils
gcc/ChangeLog:
* gcc/gimple-ssa-warn-restrict.c (builtin_memref::set_base_and_offset):
Simplify computation of the offset of the referenced subobject.
gcc/testsuite/ChangeLog:
* gcc/testsuite/gcc.dg/Warray-bounds-47.c: New test.
From-SVN: r276022
PR c++/30277
* g++.dg/expr/bitfield14.C (struct S): Use signed long long instead
of signed long.
(foo): Use long long instead of long.
From-SVN: r276021
Some changes were missed here in the transition to LRA. The Darwin
archs are all using LRA now.
gcc/ChangeLog:
2019-09-21 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.c (machopic_legitimize_pic_address): Check
for lra not reload.
From-SVN: r276020
If an insn requires two operands to be tied, and the input operand dies
in the insn, IRA acts as though there were a copy from the input to the
output with the same execution frequency as the insn. Allocating the
same register to the input and the output then saves the cost of a move.
If there is no such tie, but an input operand nevertheless dies
in the insn, IRA creates a similar move, but with an eighth of the
frequency. This helps to ensure that chains of instructions reuse
registers in a natural way, rather than using arbitrarily different
registers for no reason.
This heuristic seems to work well in the vast majority of cases.
However, for SVE, the handling of untied operands ends up creating
copies between dying predicate registers and vector outputs, even though
vector and predicate registers are distinct classes and can never be
tied. This is a particular problem because the dying predicate tends
to be the loop control predicate, which is used by most instructions
in a vector loop and so (rightly) has a very high allocation priority.
Any copies involving the loop predicate therefore tend to get processed
before copies involving only vector registers. The end result is that
we tend to allocate the output of the last vector instruction in a loop
ahead of its natural place in the allocation order and don't benefit
from chains created between vector registers.
This patch tries to avoid the problem by not adding register shuffle
copies if there appears to be no chance that the two operands could be
allocated to the same register.
2019-09-21 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* ira-conflicts.c (can_use_same_reg_p): New function.
(process_reg_shuffles): Take an insn parameter. Ignore cases
in which input operand op_num could seemingly never be allocated
to the same register as the destination.
(add_insn_allocno_copies): Update call to process_reg_shuffles.
gcc/testsuite/
* gcc.target/aarch64/sve/cond_convert_1.c: Remove XFAILs.
* gcc.target/aarch64/sve/cond_convert_4.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_2.c: Likewise.
From-SVN: r276018
This patch generalises some neg_const_int-based rtx simplifications
so that they handle all CONST_SCALAR_INTs and also CONST_POLY_INT.
This actually simplifies things a bit, since we no longer have
to treat HOST_WIDE_INT_MIN specially.
This is tested by later SVE patches.
2019-09-21 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* simplify-rtx.c (neg_const_int): Replace with...
(neg_poly_int_rtx): ...this new function.
(simplify_binary_operation_1): Extend (minus x C) -> (plus X -C)
to all CONST_SCALAR_INTs and to CONST_POLY_INT.
(simplify_plus_minus): Likewise for constant terms here.
From-SVN: r276017
This fails at m32 because the scan-asm is looking for an absence
of "ret". Darwin is generating the correct code for the function
but the picbase thunk has a 'ret' insn. Fixed by making the test
use -mdynamic-no-pic for m32.
gcc/testsuite/ChangeLog:
2019-09-20 Iain Sandoe <iain@sandoe.co.uk>
* gcc.target/i386/naked-1.c: Alter options to use non-
PIC codegen for m32 Darwin.
From-SVN: r276004
2019-09-20 Tobias Burnus <tobias@codesourcery.com>
PR fortran/78260
* openmp.c (gfc_resolve_oacc_declare): Reject all
non variables but accept function result variables.
* trans-openmp.c (gfc_trans_omp_clauses): Handle
function-result variables for remaing cases.
2019-09-20 Tobias Burnus <tobias@codesourcery.com>
PR fortran/78260
* gfortran.dg/goacc/parameter.f95: Change
dg-error as it is now detected earlier.
* gfortran.dg/goacc/pr85701.f90: Modify to
use a separate result variable.
* gfortran.dg/goacc/pr78260.f90: New.
* gfortran.dg/goacc/pr78260-2.f90: New.
* gfortran.dg/gomp/pr78260.f90: New.
* gfortran.dg/gomp/pr78260-2.f90: New.
* gfortran.dg/gomp/pr78260-3.f90: New.
From-SVN: r276002
This is causing regressions when mixing with user code compiled in ARM mode.
2019-09-20 Christophe Lyon <christophe.lyon@st.com>
Revert:
2019-09-10 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
architecture.
From-SVN: r276001
PR c/91815
* c-decl.c (pushdecl): In C detect duplicate declarations across scopes
of identifiers in the external scope only for variables and functions.
From-SVN: r275992
2019-09-20 Richard Biener <rguenther@suse.de>
PR target/91767
* config/i386/i386-features.c (general_scalar_chain::convert_registers):
Ensure there's a sequence point between allocating the new register
and passing a reference to a reg via regno_reg_rtx.
From-SVN: r275989
gcc/ChangeLog:
PR middle-end/91631
* builtins.c (component_size): Correct trailing array computation,
rename to component_ref_size and move...
(compute_objsize): Adjust.
* gimple-ssa-warn-restrict.c (builtin_memref::refsize): New member.
(builtin_access::strict): Do not consider mememmove.
(builtin_access::write_off): New function.
(builtin_memref::builtin_memref): Initialize refsize.
(builtin_memref::set_base_and_offset): Adjust refoff and compute
refsize.
(builtin_memref::offset_out_of_bounds): Use ooboff input values.
Handle refsize.
(builtin_access::builtin_access): Intialize dstoff to destination
refeence offset here instead of in maybe_diag_overlap. Adjust
referencess even to unrelated objects. Adjust sizrange of bounded
string functions to reflect bound. For strcat, adjust destination
sizrange by that of source.
(builtin_access::strcat_overlap): Adjust offsets and sizes
to reflect the increase in destination sizrange above.
(builtin_access::overlap): Do not set dstoff here but instead
in builtin_access::builtin_access.
(check_bounds_or_overlap): Use builtin_access::write_off.
(maybe_diag_access_bounds): Add argument. Add informational notes.
(dump_builtin_memref, dump_builtin_access): New functions.
* tree.c (component_ref_size): ...to here.
* tree.h (component_ref_size): Declare.
* tree-ssa-strlen (handle_builtin_strcat): Include the terminating
nul in the size of the source string.
gcc/testsuite/ChangeLog:
PR middle-end/91631
* /c-c++-common/Warray-bounds-3.c: Correct expected offsets.
* /c-c++-common/Warray-bounds-4.c: Same.
* gcc.dg/Warray-bounds-39.c: Remove xfails.
* gcc.dg/Warray-bounds-45.c: New test.
* gcc.dg/Warray-bounds-46.c: New test.
From-SVN: r275981
libcpp/ChangeLog
2019-09-19 Lewis Hyatt <lhyatt@gmail.com>
PR c/67224
* charset.c (_cpp_valid_utf8): New function to help lex UTF-8 tokens.
* internal.h (_cpp_valid_utf8): Declare.
* lex.c (forms_identifier_p): Use it to recognize UTF-8 identifiers.
(_cpp_lex_direct): Handle UTF-8 in identifiers and CPP_OTHER tokens.
Do all work in "default" case to avoid slowing down typical code paths.
Also handle $ and UCN in the default case for consistency.
gcc/Changelog
2019-09-19 Lewis Hyatt <lhyatt@gmail.com>
PR c/67224
* doc/cpp.texi: Document support for extended characters in
identifiers.
* doc/cppopts.texi: Likewise.
gcc/testsuite/ChangeLog
2019-09-19 Lewis Hyatt <lhyatt@gmail.com>
PR c/67224
* c-c++-common/cpp/ucnid-2011-1-utf8.c: New test.
* g++.dg/cpp/ucnid-1-utf8.C: New test.
* g++.dg/cpp/ucnid-2-utf8.C: New test.
* g++.dg/cpp/ucnid-3-utf8.C: New test.
* g++.dg/cpp/ucnid-4-utf8.C: New test.
* g++.dg/other/ucnid-1-utf8.C: New test.
* gcc.dg/cpp/ucnid-1-utf8.c: New test.
* gcc.dg/cpp/ucnid-10-utf8.c: New test.
* gcc.dg/cpp/ucnid-11-utf8.c: New test.
* gcc.dg/cpp/ucnid-12-utf8.c: New test.
* gcc.dg/cpp/ucnid-13-utf8.c: New test.
* gcc.dg/cpp/ucnid-14-utf8.c: New test.
* gcc.dg/cpp/ucnid-15-utf8.c: New test.
* gcc.dg/cpp/ucnid-2-utf8.c: New test.
* gcc.dg/cpp/ucnid-3-utf8.c: New test.
* gcc.dg/cpp/ucnid-4-utf8.c: New test.
* gcc.dg/cpp/ucnid-6-utf8.c: New test.
* gcc.dg/cpp/ucnid-7-utf8.c: New test.
* gcc.dg/cpp/ucnid-9-utf8.c: New test.
* gcc.dg/ucnid-1-utf8.c: New test.
* gcc.dg/ucnid-10-utf8.c: New test.
* gcc.dg/ucnid-11-utf8.c: New test.
* gcc.dg/ucnid-12-utf8.c: New test.
* gcc.dg/ucnid-13-utf8.c: New test.
* gcc.dg/ucnid-14-utf8.c: New test.
* gcc.dg/ucnid-15-utf8.c: New test.
* gcc.dg/ucnid-16-utf8.c: New test.
* gcc.dg/ucnid-2-utf8.c: New test.
* gcc.dg/ucnid-3-utf8.c: New test.
* gcc.dg/ucnid-4-utf8.c: New test.
* gcc.dg/ucnid-5-utf8.c: New test.
* gcc.dg/ucnid-6-utf8.c: New test.
* gcc.dg/ucnid-7-utf8.c: New test.
* gcc.dg/ucnid-8-utf8.c: New test.
* gcc.dg/ucnid-9-utf8.c: New test.
From-SVN: r275979
I overlooked this case when adding [[likely]] handling to
cp_parser_statement.
* parser.c (cp_parser_statement): Handle [[likely]] on
compound-statement.
From-SVN: r275978
Darwin defines '__POWERPC__' rather than '__powerpc__' so check for
the upper case version too in order to select the correct register
name.
gcc/testsuite:
2019-09-19 Iain Sandoe <iain@sandoe.co.uk>
* gcc.dg/pr89313.c: Test for __POWERPC__ in addition to
__powerpc__ in register name selection.
From-SVN: r275977
2019-09-19 Richard Biener <rguenther@suse.de>
* tree-vect-loop.c (vect_is_slp_reduction): Remove.
(check_reduction_path): New overload having the path as result.
(vect_is_simple_reduction): From the detected reduction
path build a SLP reduction chain if possible.
From-SVN: r275972
2019-09-19 Richard Biener <rguenther@suse.de>
PR target/91814
* config/i386/i386-features.c (gen_gpr_to_xmm_move_src):
Force operand to a register if it isn't nonimmediate_operand.
From-SVN: r275971
This is the libgcc part of the interface -- providing the functions.
Rationale is provided at the top of libgcc/config/aarch64/lse.S.
* config/aarch64/lse-init.c: New file.
* config/aarch64/lse.S: New file.
* config/aarch64/t-lse: New file.
* config.host: Add t-lse to all aarch64 tuples.
From-SVN: r275967
With aarch64_track_speculation, we had extra code to do exactly what the
!strong_zero_p path already did. The rest is reducing code duplication.
* config/aarch64/aarch64 (aarch64_split_compare_and_swap): Disable
strong_zero_p for aarch64_track_speculation; unify some code paths;
use aarch64_gen_compare_reg instead of open-coding.
From-SVN: r275966
This pattern will only be used with the __sync functions, because
we do not yet have a bare TImode atomic load.
* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Add support
for NE comparison of TImode values.
(aarch64_emit_load_exclusive): Add support for TImode.
(aarch64_emit_store_exclusive): Likewise.
(aarch64_split_compare_and_swap): Disable strong_zero_p for TImode.
* config/aarch64/atomics.md (@atomic_compare_and_swap<ALLI_TI>):
Change iterator from ALLI to ALLI_TI.
(@atomic_compare_and_swap<JUST_TI>): New.
(@atomic_compare_and_swap<JUST_TI>_lse): New.
(aarch64_load_exclusive_pair): New.
(aarch64_store_exclusive_pair): New.
* config/aarch64/iterators.md (JUST_TI): New.
From-SVN: r275965
2019-09-19 Feng Xue <fxue@os.amperecomputing.com>
* ipa-fnsummary.c (set_cond_stmt_execution_predicate): Do not compute
trivial predicate for condition branch.
(set_switch_stmt_execution_predicate): Do not compute trivial predicate
for switch case.
(compute_bb_predicates): Update predicate based on post-dominating
relationship.
(analyze_function_body): Calculate post-dominating information.
2019-09-19 Feng Xue <fxue@os.amperecomputing.com>
* gcc.dg/ipa/pr91089.c: Add a new function and pattern.
From-SVN: r275963
For conditional reductions, the "then" value needs to be the candidate
value calculated by this iteration while the "else" value needs to be
the result carried over from previous iterations. If the COND_EXPR
is the other way around, we need to swap it.
2019-09-19 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* tree-vectorizer.h (vectorizable_condition): Take an int
reduction index instead of a boolean flag.
* tree-vect-stmts.c (vectorizable_condition): Likewise.
Swap the "then" and "else" values for EXTRACT_LAST_REDUCTION
reductions if the reduction accumulator is the "then" rather
than the "else" value.
(vect_analyze_stmt): Update call accordingly.
(vect_transform_stmt): Likewise.
* tree-vect-loop.c (vectorizable_reduction): Likewise,
asserting that the index is > 0.
From-SVN: r275962
2019-09-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/91812
* tree-ssa-phiprop.c (propagate_with_phi): Do not replace
volatile loads.
* gcc.dg/torture/pr91812.c: New testcase.
From-SVN: r275960
This patch rewrites the way simplify_subreg handles constants.
It uses similar native_encode/native_decode routines to the
tree-level handling of VIEW_CONVERT_EXPR, meaning that we can
move between rtx constants and the target memory image of them.
The main point of this patch is to support subregs of constant-length
vectors for VLA vectors, beyond the very simple cases that were already
handled. Many of the new tests failed before the patch for variable-
length vectors.
The boolean side is tested more by the upcoming SVE ACLE work.
2019-09-19 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* defaults.h (TARGET_UNIT): New macro.
(target_unit): New type.
* rtl.h (native_encode_rtx, native_decode_rtx)
(native_decode_vector_rtx, subreg_size_lsb): Declare.
(subreg_lsb_1): Turn into an inline wrapper around subreg_size_lsb.
* rtlanal.c (subreg_lsb_1): Delete.
(subreg_size_lsb): New function.
* simplify-rtx.c: Include rtx-vector-builder.h
(simplify_immed_subreg): Delete.
(native_encode_rtx, native_decode_vector_rtx, native_decode_rtx)
(simplify_const_vector_byte_offset, simplify_const_vector_subreg): New
functions.
(simplify_subreg): Use them.
(test_vector_subregs_modes, test_vector_subregs_repeating)
(test_vector_subregs_fore_back, test_vector_subregs_stepped)
(test_vector_subregs): New functions.
(test_vector_ops): Call test_vector_subregs for integer vector
modes with at least 2 elements.
From-SVN: r275959
Emit DW_AT_GNU_bias with -fgnat-encodings=gdb. gdb implements this,
but not the encoded variant.
2019-09-19 Tom Tromey <tromey@adacore.com>
gcc/ada/
* gcc-interface/misc.c (gnat_get_type_bias): Return the bias
when -fgnat-encodings=gdb.
gcc/testsuite/
* gnat.dg/bias1.adb: New testcase.
From-SVN: r275958
In cases where pragma Annotate accepts a string literal as an argument,
we now also accept a concatenation of string literals.
2019-09-19 Steve Baird <baird@adacore.com>
gcc/ada/
* sem_prag.adb (Preferred_String_Type): A new function. Given an
expression, determines whether the preference rules defined for
the third-and-later arguments of pragma Annotate suffice to
determine the type of the expression. If so, then the preferred
type is returned; if not then Empty is returned. Handles
concatenations.
(Analyze_Pragma): Replace previous code, which dealt only with
string literals, with calls to the new Preferred_String_Type
function, which also handles concatenations.
* doc/gnat_rm/implementation_defined_pragmas.rst: Update
documentation for pragma Annotate.
* gnat_rm.texi: Regenerate.
gcc/testsuite/
* gnat.dg/annotation1.adb: New testcase.
From-SVN: r275957
This fixes a recent code quality regression for targets that do not
require the strict alignment of memory accesses: the compiler would
generate a useless temporary for a slice of an array component in an
overaligned record type.
Running these commands:
gcc -c p.adb -gnatws -gnatD
grep loop p.adb.dg
On the following sources:
procedure P (N : Positive) is
type Rec1 is record
I : Integer;
end record;
type Arr is array (Positive range <>) of Rec1;
type Rec2 is record
A : Arr (1 .. 128);
end record;
for Rec2'Alignment use 8;
procedure Proc (A : Arr) is
begin
null;
end;
R : Rec2;
begin
Proc (R.A (1 .. N));
end;
Should execute silently.
2019-09-19 Eric Botcazou <ebotcazou@adacore.com>
gcc/ada/
* exp_util.adb (Is_Possibly_Unaligned_Slice): Do not return true
on pure alignment considerations if the target does not require
the strict alignment of memory accesses.
From-SVN: r275956
