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fd118f4c54
215679 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Jerry DeLisle
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fd118f4c54 |
Fortran: Reject missing comma in format.
Standards require rejecting formats where descriptors are not separated by commas. This change allows this the missing comma to be accepted only with -std=legacy. PR fortran/88052 libgfortran/ChangeLog: * io/format.c (parse_format_list): Reject missing comma in format strings by default or if -std=f95 or higher. This is a runtime error. gcc/testsuite/ChangeLog: * gfortran.dg/comma_format_extension_4.f: Add missing comma. * gfortran.dg/dollar_edit_descriptor_2.f: Likewise. * gfortran.dg/fmt_error_9.f: Likewise. * gfortran.dg/fmt_g0_5.f08: Likewise. * gfortran.dg/fmt_t_2.f90: Likewise. * gfortran.dg/pr88052.f90: New test. |
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Maciej W. Rozycki
|
75405ead52 |
testsuite: Expand coverage for `__builtin_memcpy'
Expand coverage for `__builtin_memcpy', primarily for "cpymemM" block copy pattern, although with smaller sizes open-coded sequences may be produced instead. This verifies block sizes in bytes from 1 to 64, across byte alignments of 1, 2, 4, 8 and byte misalignments within from 0 up to 7 (there's some redundancy there for the sake of simplicity of the test cases) both for the source and the destination, making sure all data is copied and no data is changed outside the area meant to be written. These choice of the ranges for the parameters has come from the Alpha backend, whose "cpymemM" pattern covers copies being made of up to 64 bytes and has various corner cases related to base alignment and the misalignment within. The test cases have turned invaluable in verifying changes to the Alpha backend, but functionality covered is generic, so I have concluded these tests qualify for generic verification and do not have to be limited to the Alpha-specific subset of the testsuite. On the implementation side the tests turned out being quite stressful to GCC and the original simpler version that just expanded all code inline took a lot of time to complete compilation. Depending on the target and compilation options elapsed times up to 40 minutes (!) have been seen, especially with GCC built at `-O0' for debugging purposes. At the cost of increased complexity where a pair of macros is required per variant rather than just one I have split the code into individual functions forced not to be inlined and it improved compilation times considerably without losing coverage. Example compilation times with reasonably fast POWER9@2.166GHz at `-O2' optimization and GCC built at `-O2' for various targets: mips-linux-gnu: 23s vax-netbsdelf: 29s alphaev56-linux-gnu: 39s alpha-linux-gnu: 43s powerpc64le-linux-gnu: 48s With GCC built at `-O0': alphaev56-linux-gnu: 3m37s alpha-linux-gnu: 3m54s I have therefore set the timeout factor accordingly so as to take slower test hosts into account. gcc/testsuite/ * gcc.c-torture/execute/memcpy-a1.c: New file. * gcc.c-torture/execute/memcpy-a2.c: New file. * gcc.c-torture/execute/memcpy-a4.c: New file. * gcc.c-torture/execute/memcpy-a8.c: New file. * gcc.c-torture/execute/memcpy-ax.h: New file. |
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Maciej W. Rozycki
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38cbee0b3c |
build: Discard obsolete references to $(GCC_PARTS)
The $(GCC_PARTS) variable was deleted with the Makefile rework in commit |
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Jakub Jelinek
|
c4073a3d15 |
include: Add yet another DW_LANG_* enumerator from https://dwarfstd.org/languages.html
Another DW_LANG_* code has been added recently... 2024-11-23 Jakub Jelinek <jakub@redhat.com> * dwarf2.h (enum dwarf_source_language): Add DW_LANG_Fortran23 enumerator. |
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Georg-Johann Lay
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ee8e678487 |
AVR: target/117744 - Fix asm for partial clobber of address reg,
gcc/ PR target/117744 * config/avr/avr.cc (out_movqi_r_mr): Fix code when a load only partially clobbers an address register due to changing the address register temporally to accomodate for faked addressing modes. |
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Andrew Pinski
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4aa4162e36 |
md-files: Add a note about escaped quotes in braced strings in md files
While looking into PR 33532, It was noted that \" would be treated still as " for braced strings in the md file. I think that is still the correct thing to do. So let's just a note to the documentation on this behavior and NOT change read-md.cc (read_braced_string). Since this behavior has been there for the last 23 years and only one person ran into this behavior and helped with the conversion from using quoted strings to braced strings; that is you just need to remove the quote around the brace rather than change all of the code. Build the documentation to make sure it looks correct. gcc/ChangeLog: * doc/rtl.texi: Add a note about quotes in braced strings. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> |
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GCC Administrator
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8223841bda | Daily bump. | ||
Sam James
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7ff5900399
|
Sync top-level configure with binutils
This syncs us with binutils/gdb's toplevel configure as of 987db70acefd0b223a8df2240d4e5ca544cc0a91. There's not much notable here, just gprofng (which is in binutils) being disabled for musl and a new target which got added on that side too. The only part which may look interesting is the baseargs->bbaseargs change which goes back to Arsen's gettext work and a fixup which landed for that on the binutils side in 9c0aa4c53104b1c4333d55aeaf11b41053307929. * configure: Regenerate. * configure.ac: Sync with Binutils. |
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Andrew Pinski
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b3f1b9e2aa |
build: Remove INCLUDE_MEMORY [PR117737]
Since diagnostic.h is included in over half of the sources, requiring to `#define INCLUDE_MEMORY` does not make sense. Instead lets unconditionally include memory in system.h. The majority of this patch is just removing `#define INCLUDE_MEMORY` from the sources which currently have it. This should also fix the mingw build issue but I have not tried it. Bootstrapped and tested on x86_64-linux-gnu. PR bootstrap/117737 gcc/ada/ChangeLog: * gcc-interface/misc.cc (INCLUDE_MEMORY): Remove. * gcc-interface/trans.cc (INCLUDE_MEMORY): Remove. * gcc-interface/utils.cc (INCLUDE_MEMORY): Remove. gcc/analyzer/ChangeLog: * access-diagram.cc (INCLUDE_MEMORY): Remove. * analysis-plan.cc (INCLUDE_MEMORY): Remove. * analyzer-language.cc (INCLUDE_MEMORY): Remove. * analyzer-logging.cc (INCLUDE_MEMORY): Remove. * analyzer-pass.cc (INCLUDE_MEMORY): Remove. * analyzer-selftests.cc (INCLUDE_MEMORY): Remove. * analyzer.cc (INCLUDE_MEMORY): Remove. * bar-chart.cc (INCLUDE_MEMORY): Remove. * bounds-checking.cc (INCLUDE_MEMORY): Remove. * call-details.cc (INCLUDE_MEMORY): Remove. * call-info.cc (INCLUDE_MEMORY): Remove. * call-string.cc (INCLUDE_MEMORY): Remove. * call-summary.cc (INCLUDE_MEMORY): Remove. * checker-event.cc (INCLUDE_MEMORY): Remove. * checker-path.cc (INCLUDE_MEMORY): Remove. * complexity.cc (INCLUDE_MEMORY): Remove. * constraint-manager.cc (INCLUDE_MEMORY): Remove. * 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Remove. * common/config/aarch64/aarch64-common.cc (INCLUDE_MEMORY): Remove. * common/config/arm/arm-common.cc (INCLUDE_MEMORY): Remove. * common/config/avr/avr-common.cc (INCLUDE_MEMORY): Remove. * config/aarch64/aarch64-cc-fusion.cc (INCLUDE_MEMORY): Remove. * config/aarch64/aarch64-early-ra.cc (INCLUDE_MEMORY): Remove. * config/aarch64/aarch64-sve-builtins.cc (INCLUDE_MEMORY): Remove. * config/aarch64/aarch64.cc (INCLUDE_MEMORY): Remove. * config/arc/arc.cc (INCLUDE_MEMORY): Remove. * config/arm/aarch-common.cc (INCLUDE_MEMORY) Remove.: * config/arm/arm-mve-builtins.cc (INCLUDE_MEMORY): Remove. * config/arm/arm.cc (INCLUDE_MEMORY): Remove. * config/avr/avr-devices.cc (INCLUDE_MEMORY): Remove. * config/avr/driver-avr.cc (INCLUDE_MEMORY): Remove. * config/bpf/bpf.cc (INCLUDE_MEMORY): Remove. * config/bpf/btfext-out.cc (INCLUDE_MEMORY): Remove. * config/bpf/core-builtins.cc (INCLUDE_MEMORY): Remove. * config/darwin.cc (INCLUDE_MEMORY): Remove. * config/gcn/mkoffload.cc (INCLUDE_MEMORY): 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Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> |
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Jeff Law
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df2e832c90 |
[RISC-V][PR target/109279] Improve RISC-V constant synthesis
This is a small improvement to the constant synthesis code to capture a case appended to PR 109279. The case in question has the property that the high 32 bits have the value one less than the low 32 bits and the highest bit in two low 32 bits is on. The example used in BZ is 0xcccccccccccccccd which comes up computing N/10. When we construct a constant with bit 31 on, it gets implicitly sign extended. So something like 0xcccccccd when constructed would generate 0xffffffffcccccccd. The low bits are precisely what we want and the high bits are a "-1". Both properties are useful. We left shift that value by 32 positions into a temporary and add that temporary to the original value. Concretely: 0xffffffffcccccccd + 0xcccccccd00000000 ------------------ 0xcccccccccccccccd Tested in my tester on rv32 and rv64, waiting on the pre-commit tester to do its thing. PR target/109279 gcc/ * config/riscv/riscv.cc (riscv_build_integer): Handle another 64-bit synthesis where high half is one less than the low half and the 32-bit sign bit is on. gcc/testsuite/ * gcc.target/riscv/synthesis-16.c: New test. |
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Andrew Pinski
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76c2023294 |
test-art: Fix comment in types.h
The comment references INCLUDE_MEMORY but the code actually checks INCLUDE_VECTOR. So fix up the comment to mention INCLUDE_VECTROR. Pushed as obvious. gcc/ChangeLog: * text-art/types.h: Fix comment. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> |
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Georg-Johann Lay
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982d10b74b |
AVR: Tabify avr-common.cc according to coding rules.
gcc/ * common/config/avr/avr-common.cc: Tabify. |
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Georg-Johann Lay
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939362411d |
AVR: target/117726 - Tweak ashiftrt:SI and lshiftrt:SI insns.
This patch is similar to r15-5569 (tweak ashift:SI) but for ashiftrt and lshiftrt codes. It splits constant shift offsets > 16 into a 3-operand byte shift and a 2-operand residual bit shift. Moreover, some of the constraint alternatives have been promoted to 3-operand alternatives regardless of options. For example, ashift:HI and lshiftrt:HI can support 3 operands for offsets 9...12 without any overhead. Apart from that, it's a bit of code clean up for 2-byte and 4-byte shift insns: Use one RTL peephole with any_shift code iterator instead of 3 individual peepholes. It also removes some useless split insns; presumably introduced during the cc0 -> CCmode work. PR target/117726 gcc/ * config/avr/avr-passes.cc (avr_split_shift): Also handle ASHIFTRT and LSHIFTRT codes for 4-byte shifts. (constr_split_shift4): New code_attr. (avr_emit_shift): Adjust to new shift capabilities. * config/avr/predicates.md (scratch_or_d_register_operand): rename to scratch_or_dreg_operand. * config/avr/avr.md: Same. (define_peephole2): Write the RTL scratch peephole for 2-byte and 4-byte shifts that generates *sh*<mode>3_const insns using code iterator any_shift. (*ashlhi3_const_split, *ashrhi3_const_split, *ashrhi3_const_split) (*lshrsi3_const_split, *lshrhi3_const_split): Remove useless split insns. (define_split) [avropt_split_bit_shift]: Add splitters for 4-byte ASHIFTRT and LSHIFTRT insns using avr_split_shift(). (ashrsi3, *ashrsi3, *ashrsi3_const): Add "r,0,C4a" and "r,r,C4a" constraint alternatives depending on 2op, 3op. (lshrsi3, *lshrsi3, *lshrsi3_const): Add "r,0,C4r" and "r,r,C4r" constraint alternatives depending on 2op, 3op. Add "r,r,C15". (lshrhi3, *lshrhi3, *lshrhi3_const, ashlhi3, *ashlhi3) (*ashlhi3_const): Add "r,r,C7c" alternative. (ashrpsi, *ashrpsi3): Add "r,r,C22" alternative. (ashlqi, *ashlqi): Turn C06 alternative into "r,r,C06". * config/avr/constraints.md (C14, C22, C30, C7c): New constraints. * config/avr/avr.cc (ashlhi3_out, lshrhi3_out) [case 7, 9, 10, 11, 12]: Support as 3-operand insn. (lshrsi3_out) [case 15]: Same. (ashrsi3_out) [case 30]: Same. (ashrhi3_out) [case 14]: Same. (ashrqi3_out) [case 6]: Same. (avr_out_ashrpsi3) [case 22]: Same. * config/avr/avr.h: Fix comment typo. * doc/invoke.texi (AVR Options) <-msplit-bit-shift>: Document. |
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Joseph Myers
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84a335eb4f |
c: Fix typeof_unqual handling of qualified array types [PR112841]
As reported in bug 112841, typeof_unqual fails to remove qualifiers from qualified array types. In C23 (unlike in previous standard versions), array types are considered to have the qualifiers of the element type, so typeof_unqual should remove such qualifiers (and an example in the standard shows that is as intended). Fix this by calling strip_array_types when checking for the presence of qualifiers. (The reason we check for qualifiers rather than just using TYPE_MAIN_VARIANT unconditionally is to avoid, as a quality of implementation matter, unnecessarily losing typedef information in the case where the type is already unqualified.) Bootstrapped with no regressions for x86_64-pc-linux-gnu. PR c/112841 gcc/c/ * c-parser.cc (c_parser_typeof_specifier): Call strip_array_types when checking for type qualifiers for typeof_unqual. gcc/testsuite/ * gcc.dg/c23-typeof-4.c: New test. |
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Siddhesh Poyarekar
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684595188d |
tree-optimization/117355: object size for PHI nodes with negative offsets
When the object size estimate is returned for a PHI node, it is the maximum possible value, which is fine in isolation. When combined with negative offsets however, it may sometimes end up in zero size because the resultant size was larger than the wholesize, leading size_for_offset to conclude that there's a potential underflow. Fix this by allowing a non-strict mode to size_for_offset, which conservatively returns the size (or wholesize) in case of a negative offset. gcc/ChangeLog: PR tree-optimization/117355 * tree-object-size.cc (size_for_offset): New argument STRICT, return SZ if it is set to false. (plus_stmt_object_size): Adjust call to SIZE_FOR_OFFSET. gcc/testsuite/ChangeLog: PR tree-optimization/117355 * g++.dg/ext/builtin-object-size2.C (test9): New test. (main): Call it. * gcc.dg/builtin-object-size-3.c (test10): Adjust expected size. Signed-off-by: Siddhesh Poyarekar <siddhesh@gotplt.org> |
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Georg-Johann Lay
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5f95136e5e |
AVR: Use Var(avropt_xxx) for option variables in avr.opt.
This is a no-op refactoring that uses a prefix of avropt_ (formerly: avr_) for variables defined qua Var() directives in avr.opt. This makes it easier to spot values that come directly from avr.opt in the rest of the backend. gcc/ * config/avr/avr.opt (avr_bits_e, avr_lra_p, avr_mmcu) (avr_gasisr_prologues, avr_n_flash, avr_log_details) (avr_branch_cost, avr_split_bit_shift, avr_strict_X) (avr_flmap, avr_rodata_in_ram, avr_sp8, avr_fuse_add) (avr_warn_addr_space_convert, avr_warn_misspelled_isr) (avr_fuse_move, avr_double, avr_long_double): Rename to respectively: avropt_bits_e, avropt_lra_p, avropt_mmcu, avropt_gasisr_prologues, avropt_n_flash, avropt_log_details, avropt_branch_cost, avropt_split_bit_shift, avropt_strict_X, avropt_flmap, avropt_rodata_in_ram, avropt_sp8, avropt_fuse_add, avropt_warn_addr_space_convert, avropt_warn_misspelled_isr, avropt_fuse_move, avropt_double, avropt_long_double. * config/avr/avr.h: Same. * config/avr/avr.cc: Same. * config/avr/avr.md: Same. * config/avr/avr-passes.cc * config/avr/avr-log.cc: Same. * common/config/avr/avr-common.cc: Same. |
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Jakub Jelinek
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27778979c9 |
Add -f{,no-}assume-sane-operators-new-delete options [PR110137]
The following patch adds a new option for optimizations related to
replaceable global operators new/delete.
The option isn't called -fassume-sane-operator-new (which clang++
implements), because
1) clang++ option means something different; initially it was an
option to add malloc attribute to those declarations (but we have
malloc attribute on all <new> calls already unconditionally);
later it was changed to add noalias attribute rather than malloc,
whatever it means, but it is certainly about the return value
from the operator new (whether it can alias with other pointers);
we already assume malloc-ish behavior that it doesn't alias any
other pointers
2) the option only affects operator new, we want it affect also
operator delete
The option basically allows to choose between pre-PR101480 behavior
(now the default, more optimistic) and post-PR101480 behavior (safer
but penalizing most of the code in the wild for rare needs).
I've tried to explain stuff in the documentation too.
2024-11-22 Jakub Jelinek <jakub@redhat.com>
PR c++/110137
PR middle-end/101480
gcc/
* doc/invoke.texi (-fassume-sane-operators-new-delete,
-fno-assume-sane-operators-new-delete): Document.
* gimple.cc (gimple_call_fnspec): Handle
-f{,no-}assume-sane-operators-new-delete.
* ipa-inline-transform.cc (inline_call): Also clear
flag_assume_sane_operators_new_delete on caller when inlining
-fno-assume-sane-operators-new-delete callee into
-fassume-sane-operators-new-delete caller.
gcc/c-family/
* c.opt (fassume-sane-operators-new-delete): New option.
gcc/testsuite/
* g++.dg/tree-ssa/pr110137-1.C: New test.
* g++.dg/tree-ssa/pr110137-2.C: New test.
* g++.dg/tree-ssa/pr110137-3.C: New test.
* g++.dg/tree-ssa/pr110137-4.C: New test.
* g++.dg/torture/pr10148.C: Add -fno-assume-sane-operators-new-delete
as dg-additional-options.
* g++.dg/warn/Warray-bounds-16.C: Revert 2021-11-10 changes.
|
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|
Jakub Jelinek
|
c25c172959 |
match.pd: Fix up the new simpliofiers using with_possible_nonzero_bits2 [PR117420]
The following testcase shows wrong-code caused by incorrect use
of with_possible_nonzero_bits2.
That matcher is defined as
/* Slightly extended version, do not make it recursive to keep it cheap. */
(match (with_possible_nonzero_bits2 @0)
with_possible_nonzero_bits@0)
(match (with_possible_nonzero_bits2 @0)
(bit_and:c with_possible_nonzero_bits@0 @2))
and because with_possible_nonzero_bits includes the SSA_NAME case with
integral/pointer argument, both forms can actually match when a SSA_NAME
with integral/pointer type has a def stmt which is BIT_AND_EXPR
assignment with say SSA_NAME with integral/pointer type as one of its
operands (or INTEGER_CST, another with_possible_nonzero_bits case).
And in match.pd the latter actually wins if both match and so when using
(with_possible_nonzero_bits2 @0) the @0 will actually be one of the
BIT_AND_EXPR operands if that form is matched.
Now, with_possible_nonzero_bits2 and with_certain_nonzero_bits2 were added
for the
/* X == C (or X & Z == Y | C) is impossible if ~nonzero(X) & C != 0. */
(for cmp (eq ne)
(simplify
(cmp:c (with_possible_nonzero_bits2 @0) (with_certain_nonzero_bits2 @1))
(if (wi::bit_and_not (wi::to_wide (@1), get_nonzero_bits (@0)) != 0)
{ constant_boolean_node (cmp == NE_EXPR, type); })))
simplifier, but even for that one I think they do not do a good job, they
might actually pessimize stuff rather than optimize, but at least does not
result in wrong-code, because the operands are solely tested with
wi::to_wide or get_nonzero_bits, but not actually used in the
simplification. The reason why it can pessimize stuff is say if we have
# RANGE [irange] int ... MASK 0xb VALUE 0x0
x_1 = ...;
# RANGE [irange] int ... MASK 0x8 VALUE 0x0
_2 = x_1 & 0xc;
_3 = _2 == 2;
then if it used just with_possible_nonzero_bits@0, @0 would have
get_nonzero_bits (@0) 0x8 and (2 & ~8) != 0, so we can fold it into
_3 = 0;
But as it uses (with_possible_nonzero_bits2 @0), @0 is x_1 rather
than _2 and get_nonzero_bits (@0) is unnecessarily conservative,
0xb rather than 0x8 and (2 & ~0xb) == 0, so we don't optimize.
Now, with_possible_nonzero_bits2 can actually improve stuff as well in that
pattern, if say value ranges aren't fully computed yet or the BIT_AND_EXPR
assignment has been added later and the lhs doesn't have range computed yet,
get_nonzero_range on the BIT_AND_EXPR lhs will be all bits set, while
on the BIT_AND_EXPR operand might actually succeed.
I believe better would be to either modify get_nonzero_bits so that it
special cases the SSA_NAME with BIT_AND_EXPR def_stmt (but one level
deep only like with_possible_nonzero_bits2, no recursion), in that case
return bitwise and of get_nonzero_bits (non-recursive) for the lhs and
both operands, and possibly BIT_AND_EXPR itself e.g. for GENERIC
matching during by returning bitwise and of both operands.
Then with_possible_nonzero_bits2 could be needed for the GENERIC case,
perhaps have the second match #if GENERIC, but changed so that the @N
operand always is the whole thing rather than its operand which is
error-prone. Or add get_nonzero_bits wrapper with a different name
which would do that.
with_certain_nonzero_bits2 could be changed similarly, these days
we can test known non-zero bits rather than possible non-zero bits on
SSA_NAMEs too, we record both mask and value, so possible nonzero bits
(aka. get_nonzero_bits) is mask () | value (), while known nonzero bits
is value () & ~mask (), with a new function (get_known_nonzero_bits
or get_certain_nonzero_bits etc.) which handles that.
Anyway, the following patch doesn't do what I wrote above just yet,
for that single pattern it is just a missed optimization.
But the with_possible_nonzero_bits2 uses in the 3 new simplifiers are
just completely incorrect, because they don't just use the @0 operand
in get_nonzero_bits (pessimizing stuff if value ranges are fully computed),
but also use it in the replacement, then they act as if the BIT_AND_EXPR
wasn't there at all.
While we could use (with_possible_nonzero_bits2@3 @0) and use
get_nonzero_bits (@0) and use @3 in the replacement, that would still
often be a pessimization, so I've just used with_possible_nonzero_bits@0.
2024-11-22 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/117420
* match.pd ((X >> C1) << (C1 + C2) -> X << C2,
(X >> C1) * (C2 << C1) -> X * C2, X / (1 << C) -> X /[ex] (1 << C)):
Use with_possible_nonzero_bits@0 rather than
(with_possible_nonzero_bits2 @0).
* gcc.dg/torture/pr117420.c: New test.
|
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|
Jakub Jelinek
|
44984f7f75 |
c-family: Yet another fix for _BitInt & __sync_* builtins [PR117641]
Sorry, the last patch only partially fixed the __sync_* ICEs with _BitInt(128) on ia32. Even for !fetch we need to error out and return 0. I was afraid of APIs like __atomic_exchange/__atomic_compare_exchange, those obviously need to be supported even on _BitInt(128) on ia32, but they actually never sync_resolve_size, they are handled by adding the size argument and using the library version much earlier. For fetch && !orig_format (i.e. __atomic_fetch_* etc.) we need to return -1 so that we handle it with a manualy __atomic_load + __atomic_compare_exchange loop in the caller, all other cases should be rejected. 2024-11-22 Jakub Jelinek <jakub@redhat.com> PR c/117641 * c-common.cc (sync_resolve_size): For size 16 with _BitInt on targets where TImode isn't supported, use goto incompatible if !fetch. * gcc.dg/bitint-117.c: New test. |
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|
Andrew Pinski
|
cdd7171a6b |
libsanitizer: Move language level from gnu++14 to gnu++17
While compiling libsanitizer for aarch64-linux-gnu, I noticed the new warning:
```
../../../../libsanitizer/asan/asan_interceptors.cpp: In function ‘char* ___interceptor_strcpy(char*, const char*)’:
../../../../libsanitizer/asan/asan_interceptors.cpp:554:6: warning: ‘if constexpr’ only available with ‘-std=c++17’ or ‘-std=gnu++17’ [-Wc++17-extensions]
554 | if constexpr (SANITIZER_APPLE) {
| ^~~~~~~~~
```
So compile-rt upstream compiles this as gnu++17 (the current defualt for clang), so let's update it
to be similar.
Build and tested on aarch64-linux-gnu.
PR sanitizer/117731
libsanitizer/ChangeLog:
* asan/Makefile.am (AM_CXXFLAGS): Replace gnu++14 with gnu++17.
* asan/Makefile.in: Regenerate.
* hwasan/Makefile.am (AM_CXXFLAGS): Replace gnu++14 with gnu++17.
* hwasan/Makefile.in: Regenerate.
* interception/Makefile.am (AM_CXXFLAGS): Replace gnu++14 with gnu++17.
* interception/Makefile.in: Regenerate.
* libbacktrace/Makefile.am (AM_CXXFLAGS): Replace gnu++14 with gnu++17.
* libbacktrace/Makefile.in (AM_CXXFLAGS): Regenerate.
* lsan/Makefile.am (AM_CXXFLAGS): Replace gnu++14 with gnu++17.
* lsan/Makefile.in: Regenerate.
* sanitizer_common/Makefile.am (AM_CXXFLAGS): Replace gnu++14 with gnu++17.
* sanitizer_common/Makefile.in: Regenerate.
* tsan/Makefile.am (AM_CXXFLAGS): Replace gnu++14 with gnu++17.
* tsan/Makefile.in: Regenerate.
* ubsan/Makefile.am (AM_CXXFLAGS): Replace gnu++14 with gnu++17.
* ubsan/Makefile.in: Regenerate.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
|
||
Dimitar Dimitrov
|
eeff504238
|
testsuite: RISC-V: Fix vector flags handling [PR117603]
The DejaGnu routine "riscv_get_arch" fails to infer the correct
architecture string when GCC is built for RV32EC. This causes invalid
architecture string to be produced by "add_options_for_riscv_v":
xgcc: error: '-march=rv32cv': first ISA subset must be 'e', 'i' or 'g'
Fix by adding the E base ISA variant to the list of possible architecture
modifiers.
Also, the V extension is added to the machine string without checking
whether dependent extensions are available. This results in errors when
GCC is built for RV32EC:
Executing on host: .../xgcc ... -march=rv32ecv ...
cc1: error: ILP32E ABI does not support the 'D' extension
cc1: sorry, unimplemented: Currently the 'V' implementation requires the 'M' extension
Fix by disabling vector tests for RISC-V if V extension cannot be added
to current architecture.
Tested riscv32-none-elf for -march=rv32ec using GNU simulator. Most of
the remaining failures are due to explicit addition of vector options,
yet missing "dg-require-effective-target riscv_v_ok":
=== gcc Summary ===
# of expected passes 211958
# of unexpected failures 1826
# of expected failures 1059
# of unresolved testcases 5209
# of unsupported tests 15513
Ensured riscv64-unknown-linux-gnu tested with qemu has no new passing or
failing tests, before and after applying this patch:
Running target riscv-sim/-march=rv64imafdc/-mabi=lp64d/-mcmodel=medlow
...
=== gcc Summary ===
# of expected passes 237209
# of unexpected failures 335
# of expected failures 1670
# of unresolved testcases 43
# of unsupported tests 16767
PR target/117603
gcc/testsuite/ChangeLog:
* lib/target-supports.exp (riscv_get_arch): Add comment about
function purpose. Add E ISA to list of possible
modifiers.
(check_vect_support_and_set_flags): Do not advertise vector
support if V extension cannot be enabled.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
|
||
Tobias Burnus
|
f34422e06c |
OpenMP: Add 'interop' clause to 'dispatch' for C/C++
Will fail with an error if/as no suitable 'append_args' has been specified, given that 'append_args' is not yet implemented. gcc/c-family/ChangeLog: * c-pragma.h (enum pragma_omp_clause): Add PRAGMA_OMP_CLAUSE_INTEROP. gcc/c/ChangeLog: * c-parser.cc (c_parser_omp_clause_interop): New. (c_parser_omp_clause_name, c_parser_omp_all_clauses, c_parser_omp_dispatch_body): Handle 'interop' clause. * c-typeck.cc (c_finish_omp_clauses): Likewise. gcc/cp/ChangeLog: * parser.cc (cp_parser_omp_clause_name, cp_parser_omp_all_clauses, cp_parser_omp_dispatch_body): Handle 'interop' clause. * pt.cc (tsubst_omp_clauses): Likewise. * semantics.cc (finish_omp_clauses): Likewise. gcc/ChangeLog: * gimplify.cc (gimplify_call_expr): Add initial support for dispatch's 'interop' clause. (gimplify_scan_omp_clauses): Handle interop clause. * tree-pretty-print.cc (dump_omp_clause): Likewise. * tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_INTEROP. * tree.cc (omp_clause_num_ops, omp_clause_code_name): Add interop. gcc/testsuite/ChangeLog: * c-c++-common/gomp/dispatch-11.c: New test. * c-c++-common/gomp/dispatch-12.c: New test. |
||
|
Tobias Burnus
|
8f0c8e577a |
OpenMP: 'interop' construct - add C/C++ parser support, improve Fortran parsing
Add middle end support for the 'interop' directive and the 'init', 'use',
and 'destroy' clauses - but fail with a sorry, unimplemented in gimplify.cc.
For Fortran, generate the tree code, update the internal representation,
add some more diagnostic checks and update for newer specification changes
('fr' only takes a single value, but it integer expressions are permitted
again [like with the old syntax] not only constant identifiers).
For C and C++, this patch adds the full parser support for 'interop'.
Still missing is actually handling the directive in the middle end and
in libgomp.
The GOMP_INTEROP_IFR_* internal values have been changed to have space
for vendor specific values that are adjacent to the existing values
but negative, if needed.
gcc/c-family/ChangeLog:
* c-common.h (enum c_omp_region_type): Add C_ORT_INTEROP
and C_ORT_OMP_INTEROP.
(c_omp_interop_t_p): New prototype.
* c-omp.cc (c_omp_interop_t_p): Check whether the type is
omp_interop_t.
(c_omp_directives): Uncomment 'interop'.
* c-pragma.cc (omp_pragmas): Add 'interop'.
* c-pragma.h (enum pragma_kind): Add PRAGMA_OMP_INTEROP.
(enum pragma_omp_clause): Add init, use, and destroy clauses.
gcc/c/ChangeLog:
* c-parser.cc (INCLUDE_STRING): Define.
(c_parser_pragma): Handle 'interop' directive.
(c_parser_omp_clause_name): Handle init, use, and destroy clauses.
(c_parser_omp_all_clauses): Likewise; use C_ORT_OMP_INTEROP, if
'use' is permitted, for c_finish_omp_clauses.
(c_parser_omp_clause_destroy, c_parser_omp_modifier_prefer_type,
c_parser_omp_clause_init, c_parser_omp_clause_use,
OMP_INTEROP_CLAUSE_MASK, c_parser_omp_interop): New.
* c-typeck.cc (c_finish_omp_clauses): Add missing OPT_Wopenmp to
a warning; handle new clauses.
gcc/cp/ChangeLog:
* parser.cc (INCLUDE_STRING): Define.
(cp_parser_omp_clause_name): Handle init, use, and destroy clauses.
(cp_parser_omp_all_clauses): Likewise; use C_ORT_OMP_INTEROP, if
'use' is permitted, for c_finish_omp_clauses.
(cp_parser_omp_modifier_prefer_type, cp_parser_omp_clause_init,
OMP_INTEROP_CLAUSE_MASK, cp_parser_omp_interop): New.
(cp_parser_pragma): Handle 'interop' directive.
* pt.cc (tsubst_omp_clauses): Handle init, use, and destroy clauses.
(tsubst_stmt): Handle OMP_INTEROP.
* semantics.cc (cp_omp_init_prefer_type_update): New.
(finish_omp_clauses): Handle init, use, and destroy clauses
and add clause check for 'depend' on 'interop'.
gcc/fortran/ChangeLog:
* gfortran.h (gfc_omp_namelist): Cleanup interop internal
representation.
* dump-parse-tree.cc (show_omp_namelist): Update for changed
internal representation.
* match.cc (gfc_free_omp_namelist): Likewise.
* openmp.cc (gfc_match_omp_prefer_type, gfc_match_omp_init):
Likewise; also handle some corner cases better and update for
newer 6.0 changes related to 'fr'.
(resolve_omp_clauses): Add type-check for interop variables.
* trans-openmp.cc (gfc_trans_omp_clauses): Handle init, use
and destroy clauses.
(gfc_trans_openmp_interop): New.
(gfc_trans_omp_directive): Call it.
gcc/ChangeLog:
* gimplify.cc (gimplify_expr): Handle OMP_INTEROP by printing
"sorry, uninplemented".
* omp-api.h (omp_get_fr_id_from_name): Change return type to
'char'.
* omp-general.cc (omp_get_fr_id_from_name): Likewise; return
GOMP_INTEROP_IFR_UNKNOWN not 0 if not found.
(omp_get_name_from_fr_id): Return "<unknown>" not NULL
if not found (used for dumps).
* tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_DESTROY,
OMP_CLAUSE_USE, and OMP_CLAUSE_INIT.
* tree-pretty-print.cc (dump_omp_init_prefer_type): New.
(dump_omp_clause): Handle init, use and destroy clauses.
(dump_generic_node): Handle interop directive.
* tree.cc (omp_clause_num_ops, omp_clause_code_name): Add new
init/use/destroy clauses.
* tree.def (OACC_LOOP): Fix comment.
(OMP_INTEROP): Add.
* tree.h (OMP_INTEROP_CLAUSES, OMP_CLAUSE_INIT_TARGET,
OMP_CLAUSE_INIT_TARGETSYNC, OMP_CLAUSE_INIT_PREFER_TYPE): New.
include/ChangeLog:
* gomp-constants.h (GOMP_INTEROP_IFR_NONE): Rename ...
(GOMP_INTEROP_IFR_UNKNOWN): ... to this. And change value.
(GOMP_INTEROP_IFR_SEPARATOR): Likewise.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/interop-1.f90: Update for parser changes,
spec changes and add new tests.
* gfortran.dg/gomp/interop-2.f90: Likewise.
* gfortran.dg/gomp/interop-3.f90: Likewise.
* c-c++-common/gomp/interop-1.c: New test.
* c-c++-common/gomp/interop-2.c: New test.
* c-c++-common/gomp/interop-3.c: New test.
* c-c++-common/gomp/interop-4.c: New test.
* g++.dg/gomp/interop-5.C: New test.
* gfortran.dg/gomp/interop-4.f90: New test.
|
||
Evgeny Karpov
|
8d7f2d53c8 |
MAINTAINERS: Add myself to write after approval
ChangeLog: * MAINTAINERS: Add myself to write after approval. |
||
|
Jakub Jelinek
|
d6d1fdcf95 |
i386: Make __builtin_ia32_f{nstenv,ldenv,nstsw,fnclex} builtins internal [PR117165]
As the comment says, these builtins are meant to be internal for the atomic support and cause various ICEs when using them directly in various conditions. So the following patch makes them internal. We do have also internal-fn.*, but those target specific builtins would need to be there in generic code, so I've just added space to their name, which is the old way to hide builtins/attributes etc. 2024-11-22 Jakub Jelinek <jakub@redhat.com> PR target/117165 * config/i386/i386-builtin.def (IX86_BUILTIN_FNSTENV, IX86_BUILTIN_FLDENV, IX86_BUILTIN_FNSTSW, IX86_BUILTIN_FNCLEX): Add space to the end of the builtin name to make it really internal. * gcc.target/i386/pr117165.c: New test. |
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|
Jakub Jelinek
|
77f4b1097e |
testsuite: Fix up vector-{8,9,10}.c tests
On Thu, Nov 21, 2024 at 01:30:39PM +0100, Christoph Müllner wrote: > > > * gcc.dg/tree-ssa/satd-hadamard.c: New test. > > > * gcc.dg/tree-ssa/vector-10.c: New test. > > > * gcc.dg/tree-ssa/vector-8.c: New test. > > > * gcc.dg/tree-ssa/vector-9.c: New test. I see FAILs on i686-linux or on x86_64-linux (in the latter with -m32 testing). One problem is that vector-10.c doesn't use -Wno-psabi option and uses a function which returns a vector and takes vector as first parameter, the other problems are that 3 other tests don't arrange for at least basic vector ISA support, plus non-standardly test only on x86_64-*-*, while normally one would allow both i?86-*-* x86_64-*-* and if it is e.g. specific to 64-bit, also check for lp64 or int128 or whatever else is needed. E.g. Solaris I think has i?86-*-* triplet even for 64-bit code, etc. The following patch fixes these. 2024-11-22 Jakub Jelinek <jakub@redhat.com> * gcc.dg/tree-ssa/satd-hadamard.c: Add -msse2 as dg-additional-options on x86. Also scan-tree-dump on i?86-*-*. * gcc.dg/tree-ssa/vector-8.c: Likewise. * gcc.dg/tree-ssa/vector-9.c: Likewise. * gcc.dg/tree-ssa/vector-10.c: Add -Wno-psabi to dg-additional-options. |
||
Tamar Christina
|
a9473f9c6f |
middle-end:For multiplication try swapping operands when matching complex multiply [PR116463]
This commit fixes the failures of complex.exp=fast-math-complex-mls-*.c on the
GCC 14 branch and some of the ones on the master.
The current matching just looks for one order for multiplication and was relying
on canonicalization to always give the right order because of the TWO_OPERANDS.
However when it comes to the multiplication trying only one order is a bit
fragile as they can be flipped.
The failing tests on the branch are:
void fms180snd(_Complex TYPE a[restrict N], _Complex TYPE b[restrict N],
_Complex TYPE c[restrict N]) {
for (int i = 0; i < N; i++)
c[i] -= a[i] * (b[i] * I * I);
}
void fms180fst(_Complex TYPE a[restrict N], _Complex TYPE b[restrict N],
_Complex TYPE c[restrict N]) {
for (int i = 0; i < N; i++)
c[i] -= (a[i] * I * I) * b[i];
}
The issue is just a small difference in commutative operations.
we look for {R,R} * {R,I} but found {R,I} * {R,R}.
Since the DF analysis is cached, we should be able to swap operands and retry
for multiply cheaply.
There is a constraint being checked by vect_validate_multiplication for the data
flow of the operands feeding the multiplications. So e.g.
between the nodes:
note: node 0x4d1d210 (max_nunits=2, refcnt=3) vector(2) double
note: op template: _27 = _10 * _25;
note: stmt 0 _27 = _10 * _25;
note: stmt 1 _29 = _11 * _25;
note: node 0x4d1d060 (max_nunits=2, refcnt=2) vector(2) double
note: op template: _26 = _11 * _24;
note: stmt 0 _26 = _11 * _24;
note: stmt 1 _28 = _10 * _24;
we require the lanes to come from the same source which
vect_validate_multiplication checks. As such it doesn't make sense to flip them
individually because that would invalidate the earlier linear_loads_p checks
which have validated that the arguments all come from the same datarefs.
This patch thus flips the operands in unison to still maintain this invariant,
but also honor the commutative nature of multiplication.
gcc/ChangeLog:
PR tree-optimization/116463
* tree-vect-slp-patterns.cc (complex_mul_pattern::matches,
complex_fms_pattern::matches): Try swapping operands on multiply.
|
||
Lulu Cheng
|
9286411658 |
LoongArch: Modify the document to remove options that don't exist.
gcc/ChangeLog: * doc/invoke.texi: Remove the non-existent option '-msmall-data-limit' and add a description of '-G'. |
||
|
Lulu Cheng
|
a3a375b2d1 |
LoongArch: Remove redundant code.
TARGET_ASM_ALIGNED_{HI,SI,QI}_OP are defined repeatedly and deleted.
gcc/ChangeLog:
* config/loongarch/loongarch-builtins.cc
(loongarch_builtin_vectorized_function): Delete.
(LARCH_GET_BUILTIN): Delete.
* config/loongarch/loongarch-protos.h
(loongarch_builtin_vectorized_function): Delete.
* config/loongarch/loongarch.cc
(TARGET_ASM_ALIGNED_HI_OP): Delete.
(TARGET_ASM_ALIGNED_SI_OP): Delete.
(TARGET_ASM_ALIGNED_DI_OP): Delete.
|
||
Haochen Jiang
|
45135f9d5f |
i386/testsuite: Enhance AVX10.2 vmovd/w testcases
Under -fno-omit-frame-pointer, %ebp will be used, which is the Solaris/x86 default. Both check %ebp and %esp to avoid error on that. gcc/testsuite/ChangeLog: PR target/117697 * gcc.target/i386/avx10_2-vmovd-1.c: Both check %esp and %ebp. * gcc.target/i386/avx10_2-vmovw-1.c: Ditto. |
||
|
Lulu Cheng
|
f0cb64fb3f |
LoongArch: Fix clerical errors in lasx_xvreplgr2vr_* and lsx_vreplgr2vr_*.
[x]vldi.{b/h/w/d} is not implemented in LoongArch.
Use the macro [x]vrepli.{b/h/w/d} to replace.
gcc/ChangeLog:
* config/loongarch/lasx.md: Fixed.
* config/loongarch/lsx.md: Fixed.
|
||
Xi Ruoyao
|
ae7e25662f |
LoongArch: Make __builtin_lsx_vorn_v and __builtin_lasx_xvorn_v arguments and return values unsigned
Align them with other vector bitwise builtins. This may break programs directly invoking __builtin_lsx_vorn_v or __builtin_lasx_xvorn_v, but doing so is not supported (as builtins are not documented, only intrinsics are documented and users should use them instead). gcc/ChangeLog: * config/loongarch/loongarch-builtins.cc (vorn_v, xvorn_v): Use unsigned vector modes. * config/loongarch/lsxintrin.h (__lsx_vorn_v): Cast arguments to v16u8. * config/loongarch/lasxintrin.h (__lasx_xvorn_v): Cast arguments to v32u8. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-builtin.c (__lsx_vorn_v): Change arguments and return value to v16u8. * gcc.target/loongarch/vector/lasx/lasx-builtin.c (__lasx_xvorn_v): Change arguments and return value to v32u8. |
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GCC Administrator
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8500a8c32b | Daily bump. | ||
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Jeff Law
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9b7917b34f |
[RISC-V][PR target/117690] Add missing shift in constant synthesis
As hinted out in the BZ, we were missing a left shift in the constant synthesis in the case where the upper 32 bits can be synthesized using a shNadd of the low 32 bits. This adjusts the synthesis to add the missing left shift and adjusts the cost to account for the additional instruction. Regression tested on riscv64-elf in my tester. Waiting for the pre-commit tester before moving forward. PR target/117690 gcc/ * config/riscv/riscv.cc (riscv_build_integer): Add missing left shift when using shNadd to derive upper 32 bits from lower 32 bits. gcc/testsuite * gcc.target/riscv/pr117690.c: New test. * gcc.target/riscv/synthesis-13.c: Adjust expected output. |
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Arsen Arsenović
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ffeee625c5
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doc/cpp: Document __has_include_next
While hacking on an unrelated change, I noticed that __has_include_next hasn't been documented at all. This patch adds it to the __has_include manual node. gcc/ChangeLog: * doc/cpp.texi (__has_include): Document __has_include_next also. (Conditional Syntax): Mention __has_include_next in the description for the __has_include menu entry. |
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Joseph Myers
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338d687e2a |
c: Give errors more consistently for void parameters [PR114816]
Cases of void parameters, other than a parameter list of (void) (or equivalent with a typedef for void) in its entirety, have been made a constraint violation in C2Y (N3344 alternative 1 was adopted), as part of a series of changes to eliminate unnecessary undefined behavior by turning it into constraint violations, implementation-defined behavior or something else with stricter bounds on what behavior is allowed. Previously, these were implicitly undefined behavior (see DR#295), with only some cases listed in Annex J as undefined (but even those cases not having wording in the normative text to make them explicitly undefined). As discussed in bug 114816, GCC is not entirely consistent about diagnosing such usages; unnamed void parameters get errors when not the entire parameter list, while qualified and register void (the cases listed in Annex J) get errors as a single unnamed parameter, but named void parameters are accepted with a warning (in a declaration that's not a definition; it's not possible to define a function with incomplete parameter types). Following C2Y, make all these cases into errors. The errors are not conditional on the standard version, given that this was previously implicit undefined behavior. Since it wasn't possible anyway to define such functions, only declare them without defining them (or otherwise use such parameters in function type names that can't correspond to any defined function), hopefully the risks of compatibility issues are small. Bootstrapped with no regressions for x86-64-pc-linux-gnu. PR c/114816 gcc/c/ * c-decl.cc (grokparms): Do not warn for void parameter type here. (get_parm_info): Give errors for void parameters even when named. gcc/testsuite/ * gcc.dg/c2y-void-parm-1.c: New test. * gcc.dg/noncompile/920616-2.c, gcc.dg/noncompile/921116-1.c, gcc.dg/parm-incomplete-1.c: Update expected diagnostics. |
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David Malcolm
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4574f15bb3 |
json parsing: avoid relying on floating point equality [PR117677]
gcc/ChangeLog: PR bootstrap/117677 * json-parsing.cc (selftest::test_parse_number): Replace ASSERT_EQ of 'double' values with ASSERT_NEAR. Eliminate ASSERT_PRINT_EQ for such values. * selftest.h (ASSERT_NEAR): New. (ASSERT_NEAR_AT): New. Signed-off-by: David Malcolm <dmalcolm@redhat.com> |
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David Malcolm
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b599498e18 |
testsuite: add print-stack.exp
I wrote this support file to help me debug Tcl issues in the
testsuite.
Adding a call to:
print_stack_backtrace
somewhere in a .exp file (along with "load_lib print-stack.exp") leads
to the interpreter printing a backtrace in a form that e.g. Emacs can
consume, with filename:linenum: lines, and quoting the line of .exp
source code.
Fer example, adding a print_stack_backtrace to scansarif.exp in
run-sarif-pytest I get this output:
VVV START OF BACKTRACE VVV
/home/david/coding/gcc-newgit/src/gcc/testsuite/lib/scansarif.exp:142: frame 16 in proc print_stack_backtrace
142 | print_stack_backtrace
<proc>: frame 15 in proc run-sarif-pytest
<eval>: frame 14 in proc dg-final-proc
/usr/share/dejagnu/dg.exp:851: frame 13 in proc dg-final-proc
851 | if {[catch "dg-final-proc $prog" errmsg]} {
<eval>: frame 12 in proc saved-dg-test
/home/david/coding/gcc-newgit/src/gcc/testsuite/lib/gcc-dg.exp:1080: frame 11 in proc saved-dg-test
1080 | if { [ catch { eval saved-dg-test $args } errmsg ] } {
/usr/share/dejagnu/dg.exp:559: frame 10 in proc dg-test
559 | dg-test $testcase $options ${default-extra-options}
/home/david/coding/gcc-newgit/src/gcc/testsuite/gcc.dg/sarif-output/sarif-output.exp:28: frame 9
28 | dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] "" ""
<eval>: frame 8
<eval>: frame 7
/usr/share/dejagnu/runtest.exp:1460: frame 6
1460 | if { [catch "uplevel #0 source $test_file_name"] == 1 } {
/usr/share/dejagnu/runtest.exp:1886: frame 5 in proc dg-runtest
1886 | runtest $test_name
/usr/share/dejagnu/runtest.exp:1845: frame 4 in proc dg-runtest
1845 | foreach test_name [lsort [find ${dir} *.exp]] {
/usr/share/dejagnu/runtest.exp:1788: frame 3 in proc dg-runtest
1788 | foreach dir "${test_top_dirs}" {
/usr/share/dejagnu/runtest.exp:1669: frame 2 in proc dg-runtest
1669 | foreach pass $multipass {
/usr/share/dejagnu/runtest.exp:1619: frame 1 in proc dg-runtest
1619 | foreach current_target $target_list {
^^^ END OF BACKTRACE ^^^
and can click on the lines in Emacs's compilation buffer to take
me to the relevant places.
I found this made it *much* easier to debug my .exp files. That
said, I'm uncomfortable with Tcl, and so
(a) there may be a better way of doing this
(b) I may have made mistakes
gcc/testsuite/ChangeLog:
* lib/print-stack.exp: New file.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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Christoph Müllner
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ae0d842f3e |
testsuite: tree-ssa: Limit targets for vec perm tests
Recently added test cases assume optimized code generation for certain vectorized code. However, this optimization might not be applied if the backends don't support the optimized permuation. The tests are confirmed to work on aarch64 and x86-64, so this patch restricts the tests accordingly. Tested on x86-64. PR117728 gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/satd-hadamard.c: Restrict to aarch64 and x86-64. * gcc.dg/tree-ssa/vector-8.c: Likewise. * gcc.dg/tree-ssa/vector-9.c: Likewise. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> |
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Jason Merrill
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819f67a2f6 |
c++: inline variables and modules
We weren't writing out the definition of an inline variable, so the importer either got an undefined symbol or 0. gcc/cp/ChangeLog: * module.cc (has_definition): Also true for inline vars. gcc/testsuite/ChangeLog: * g++.dg/modules/inline-1_a.C: New test. * g++.dg/modules/inline-1_b.C: New test. |
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Jason Merrill
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74498be0e6 |
c++: modules and debug marker stmts
21_strings/basic_string/operations/contains/nonnull.cc was failing because the module was built with debug markers and the testcase was built not expecting debug markers, so we crashed in lower_stmt. Let's accommodate this by discarding debug marker statements we don't want. gcc/cp/ChangeLog: * module.cc (trees_in::core_vals) [STATEMENT_LIST]: Skip DEBUG_BEGIN_STMT if !MAY_HAVE_DEBUG_MARKER_STMTS. |
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Jason Merrill
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03c7145a41 |
c++: modules and tsubst_friend_class
In 20_util/function_objects/mem_fn/constexpr.cc we start to instantiate _Mem_fn_base's friend declaration of _Bind_check_arity before we've loaded the namespace-scope declaration, so lookup_imported_hidden_friend doesn't find it. But then we load the namespace-scope declaration in lookup_template_class during substitution, and so when we get around to pushing the result of substitution, they conflict. Fixed by calling lazy_load_pendings in lookup_imported_hidden_friend. gcc/cp/ChangeLog: * name-lookup.cc (lookup_imported_hidden_friend): Call lazy_load_pendings. |
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Georg-Johann Lay
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873cffc792 |
AVR: target/117726 - Better optimizations of ASHIFT:SI insns.
This patch improves the 4-byte ASHIFT insns. 1) It adds a "r,r,C15" alternative for improved long << 15. 2) It adds 3-operand alternatives (depending on options) and splits them after peephole2 / before avr-fuse-move into a 3-operand byte shift and a 2-operand residual bit shift. For better control, it introduces new option -msplit-bit-shift that's activated at -O2 and higher per default. 2) is even performed with -Os, but not with -Oz. PR target/117726 gcc/ * config/avr/avr.opt (-msplit-bit-shift): Add new optimization option. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_2_PLUS]: Turn on -msplit-bit-shift. * config/avr/avr.h (machine_function.n_avr_fuse_add_executed): New bool component. * config/avr/avr.md (attr "isa") <2op, 3op>: Add new values. (attr "enabled"): Handle them. (ashlsi3, *ashlsi3, *ashlsi3_const): Add "r,r,C15" alternative. Add "r,0,C4l" and "r,r,C4l" alternatives (depending on 2op / 3op). (define_split) [avr_split_bit_shift]: Add 2 new ashift:ALL4 splitters. (define_peephole2) [ashift:ALL4]: Add (match_dup 3) so that the scratch won't overlap with the output operand of the matched insn. (*ashl<mode>3_const_split): Remove unused ashift:ALL4 splitter. * config/avr/avr-passes.cc (emit_valid_insn) (emit_valid_move_clobbercc): Move out of anonymous namespace. (make_avr_pass_fuse_add) <gate>: Don't override. <execute>: Set n_avr_fuse_add_executed according to func->machine->n_avr_fuse_add_executed. (pass_data avr_pass_data_split_after_peephole2): New object. (avr_pass_split_after_peephole2): New rtl_opt_pass. (avr_emit_shift): New static function. (avr_shift_is_3op, avr_split_shift_p, avr_split_shift) (make_avr_pass_split_after_peephole2): New functions. * config/avr/avr-passes.def (avr_pass_split_after_peephole2): Insert new pass after pass_peephole2. * config/avr/avr-protos.h (n_avr_fuse_add_executed, avr_shift_is_3op, avr_split_shift_p) (avr_split_shift, avr_optimize_size_level) (make_avr_pass_split_after_peephole2): New prototypes. * config/avr/avr.cc (n_avr_fuse_add_executed): New global variable. (avr_optimize_size_level): New function. (avr_set_current_function): Set n_avr_fuse_add_executed according to cfun->machine->n_avr_fuse_add_executed. (ashlsi3_out) [case 15]: Output optimized code for this offset. (avr_rtx_costs_1) [ASHIFT, SImode]: Adjust costs of oggsets 15, 16. * config/avr/constraints.md (C4a, C4r, C4r): New constraints. * pass_manager.h (pass_manager): Adjust comments. |
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Georg-Johann Lay
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938094abec |
AVR: Fix a nit in avr-passes.cc::absint_t.dump().
gcc/ * config/avr/avr-passes.cc (absint_t::dump): Fix missing newline in dump. |
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Jeff Law
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41fb3a5669 |
[RISC-V][PR target/116590] Avoid emitting multiple instructions from fmacc patterns
So much like my patch from last week, this removes alternatives that create multiple instructions that we really should have never needed. In this case it fixes one of two bugs in pr116590. In particular we don't want vmvNr instructions for thead-vector. Those instructions were emitted as part of those two instruction sequences. I've tested this in my tester and assuming the pre-commit tester is happy, I'll push it to the trunk. PR target/116590 gcc * config/riscv/vector.md (pred_mul_<optab>mode_undef): Drop unnecessary alternatives. (pred_<madd_msub><mode>): Likewise. (pred_<macc_msac><mode>): Likewise. (pred_<madd_msub><mode>_scalar): Likewise. (pred_<macc_msac><mode>_scalar): Likewise. (pred_mul_neg_<optab><mode>_undef): Likewise. (pred_<nmsub_nmadd><mode>): Likewise. (pred_<nmsac_nmacc><mode>): Likewise. (pred_<nmsub_nmadd><mode>_scalar): Likewise. (pred_<nmsac_nmacc><mode>_scalar): Likewise. gcc/testsuite * gcc.target/riscv/pr116590.c: New test. |
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Pan Li
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fbca864a7b |
Match: Refactor the unsigned SAT_ADD match pattern [NFC]
This patch would like to refactor the unsigned SAT_ADD pattern by: * Extract type check outside. * Extract common sub pattern. * Re-arrange the related match pattern forms together. * Remove unnecessary helper pattern matches. The below test suites are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * match.pd: Refactor sorts of unsigned SAT_ADD match pattern. Signed-off-by: Pan Li <pan2.li@intel.com> Signed-off-by: Pan Li <pan2.li@intel.com> |
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Tamar Christina
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dbc38dd9e9 |
middle-end: Pass along SLP node when costing vector loads/stores
With the support to SLP only we now pass the VMAT through the SLP node, however the majority of the costing calls inside vectorizable_load and vectorizable_store do no pass the SLP node along. Due to this the backend costing never sees the VMAT for these cases anymore. Additionally the helper around record_stmt_cost when both SLP and stmt_vinfo are passed would only pass the SLP node along. However the SLP node doesn't contain all the info available in the stmt_vinfo and we'd have to go through the SLP_TREE_REPRESENTATIVE anyway. As such I changed the function to just Always pass both along. Unlike the VMAT changes, I don't believe there to be a correctness issue here but would minimize the number of churn in the backend costing until vectorizer costing as a whole is revisited in GCC 16. These changes re-enable the cost model on AArch64 and also correctly find the VMATs on loads and stores fixing testcases such as sve_iters_low_2.c. gcc/ChangeLog: * tree-vect-data-refs.cc (vect_get_data_access_cost): Pass NULL for SLP node. * tree-vect-stmts.cc (record_stmt_cost): Expose. (vect_get_store_cost, vect_get_load_cost): Extend with SLP node. (vectorizable_store, vectorizable_load): Pass SLP node to all costing. * tree-vectorizer.h (record_stmt_cost): Always pass both SLP node and stmt_vinfo to costing. (vect_get_load_cost, vect_get_store_cost): Extend with SLP node. |
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Rainer Orth
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116b1c5489 |
Use decl size in Solaris ASM_DECLARE_OBJECT_NAME [PR102296]
Solaris has modified versions of ASM_DECLARE_OBJECT_NAME on both i386
and sparc. When
commit
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Christoph Müllner
|
1c4d39ada3 |
forwprop: Try to blend two isomorphic VEC_PERM sequences
This extends forwprop by yet another VEC_PERM optimization:
It attempts to blend two isomorphic vector sequences by using the
redundancy in the lane utilization in these sequences.
This redundancy in lane utilization comes from the way how specific
scalar statements end up vectorized: two VEC_PERMs on top, binary operations
on both of them, and a final VEC_PERM to create the result.
Here is an example of this sequence:
v_in = {e0, e1, e2, e3}
v_1 = VEC_PERM <v_in, v_in, {0, 2, 0, 2}>
// v_1 = {e0, e2, e0, e2}
v_2 = VEC_PERM <v_in, v_in, {1, 3, 1, 3}>
// v_2 = {e1, e3, e1, e3}
v_x = v_1 + v_2
// v_x = {e0+e1, e2+e3, e0+e1, e2+e3}
v_y = v_1 - v_2
// v_y = {e0-e1, e2-e3, e0-e1, e2-e3}
v_out = VEC_PERM <v_x, v_y, {0, 1, 6, 7}>
// v_out = {e0+e1, e2+e3, e0-e1, e2-e3}
To remove the redundancy, lanes 2 and 3 can be freed, which allows to
change the last statement into:
v_out' = VEC_PERM <v_x, v_y, {0, 1, 4, 5}>
// v_out' = {e0+e1, e2+e3, e0-e1, e2-e3}
The cost of eliminating the redundancy in the lane utilization is that
lowering the VEC PERM expression could get more expensive because of
tighter packing of the lanes. Therefore this optimization is not done
alone, but in only in case we identify two such sequences that can be
blended.
Once all candidate sequences have been identified, we try to blend them,
so that we can use the freed lanes for the second sequence.
On success we convert 2x (2x BINOP + 1x VEC_PERM) to
2x VEC_PERM + 2x BINOP + 2x VEC_PERM traded for 4x VEC_PERM + 2x BINOP.
The implemented transformation reuses (rewrites) the statements
of the first sequence and the last VEC_PERM of the second sequence.
The remaining four statements of the second statment are left untouched
and will be eliminated by DCE later.
This targets x264_pixel_satd_8x4, which calculates the sum of absolute
transformed differences (SATD) using Hadamard transformation.
We have seen 8% speedup on SPEC's x264 on a 5950X (x86-64) and 7%
speedup on an AArch64 machine.
Bootstrapped and reg-tested on x86-64 and AArch64 (all languages).
gcc/ChangeLog:
* tree-ssa-forwprop.cc (struct _vec_perm_simplify_seq): New data
structure to store analysis results of a vec perm simplify sequence.
(get_vect_selector_index_map): Helper to get an index map from the
provided vector permute selector.
(recognise_vec_perm_simplify_seq): Helper to recognise a
vec perm simplify sequence.
(narrow_vec_perm_simplify_seq): Helper to pack the lanes more
tight.
(can_blend_vec_perm_simplify_seqs_p): Test if two vec perm
sequences can be blended.
(calc_perm_vec_perm_simplify_seqs): Helper to calculate the new
permutation indices.
(blend_vec_perm_simplify_seqs): Helper to blend two vec perm
simplify sequences.
(process_vec_perm_simplify_seq_list): Helper to process a list
of vec perm simplify sequences.
(append_vec_perm_simplify_seq_list): Helper to add a vec perm
simplify sequence to the list.
(pass_forwprop::execute): Integrate new functionality.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/satd-hadamard.c: New test.
* gcc.dg/tree-ssa/vector-10.c: New test.
* gcc.dg/tree-ssa/vector-8.c: New test.
* gcc.dg/tree-ssa/vector-9.c: New test.
* gcc.target/aarch64/sve/satd-hadamard.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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H.J. Lu
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42a8005c63 |
apx-ndd-tls-1[ab].c: Add -std=gnu17
Since GCC 15 defaults to -std=gnu23, add -std=gnu17 to apx-ndd-tls-1[ab].c to avoid: gcc.target/i386/apx-ndd-tls-1a.c: In function ‘k’: gcc.target/i386/apx-ndd-tls-1a.c:29:7: error: too many arguments to function ‘l’ gcc.target/i386/apx-ndd-tls-1a.c:25:5: note: declared here * gcc.target/i386/apx-ndd-tls-1a.c: -std=gnu17. * gcc.target/i386/apx-ndd-tls-1b.c: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com> |