* cpppch.c (reset_ht): Remove.
(cpp_read_state): Remove loop to reset hashtable identifiers.
* ggc-common.c (gt_pch_save): Add call to gt_pch_fixup_stringpool
after pch file is written.
* ggc.h (gt_pch_fixup_stringpool): Declare.
* stringpool.c (ht_copy_and_clear): Define. Callback. Copy
hashnode's value to another hashtable, then clear the original.
(saved_ident_hash): Define.
(gt_pch_save_stringpool): Create saved_ident_hash, use it to
store definitions in ident_hash, and clear ident_hash.
(gt_pch_fixup_stringpool): Define. Restore definitions from
saved_ident_hash to ident_hash, then destroy saved_ident_hash.
From-SVN: r65215
PR optimization/10157
* gcse.c (can_copy_p): Rename it to can_copy.
(can_copy_init_p): Remove.
(compute_can_copy): Use can_copy instead of can_copy_p.
(can_copy_p): New exported function. Call compute_can_copy.
(hash_scan_set): Use it.
(gcse_main): Don't call compute_can_copy.
(bypass_jumps): Don't call compute_can_copy.
* rtl.h (can_copy_p): Declare.
* loop.c (scan_loop): Don't move the source and add a reg-to-reg
copy if the mode doesn't support copy operations.
From-SVN: r65210
* stor-layout.c (do_type_align): New fn, split out from...
(layout_decl): ...here. Do all alignment calculations for
FIELD_DECLs here.
(update_alignment_for_field): Not here.
(start_record_layout, debug_rli): Remove unpadded_align.
* tree.h (struct record_layout_info_s): Remove unpadded_align.
* c-decl.c (finish_enum): Don't set DECL_SIZE, DECL_ALIGN
or DECL_MODE on the CONST_DECLs.
(finish_struct): Don't mess with DECL_ALIGN.
* cp/class.c (build_vtable): Set DECL_ALIGN here.
(get_vtable_decl): Not here.
(layout_vtable_decl): Or here.
(create_vtable_ptr): Or here.
(layout_class_type): Or here.
(check_bitfield_decl): Don't mess with field alignment.
* ada/misc.c (gnat_adjust_rli): #if 0.
From-SVN: r65207
* config/h8300/h8300-protos.h: Add a prototype for
gtle_operator.
* config/h8300/h8300.c (gtle_operator): New.
* config/h8300/h8300.h (PREDICATE_CODES): Add an entry for
gtle_operator.
* config/h8300/h8300.md (a peephole2): Generalize to accept GT
and LE.
From-SVN: r65192
* i386.c (override_options): Disable red zone by default on i386.
(compute_frame_layout, ix86_force_to_memory, ix86_free_from_memory):
Do not test TARGET_64BIT together with TARGET_RED_ZONE
From-SVN: r65178
* config/rs6000/rs6000.c
(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Redefine the
macros.
(rs6000_issue_rate): Add case for 8540.
(rs6000_use_sched_lookahead): New function.
* config/rs6000/8540.md: Rename SIU units into SU ones and MIU
units into MU ones.
(ppc8540_branch, ppc8540_cr_logical): Add one cycle in the
reservation before retirement.
(ppc8540_multiply, ppc8540_load, ppc8540_store,
ppc8540_simple_float, ppc8540_vector_load, ppc8540_vector_store):
Remove additional cycle in the reservation before retirement.
(ppc8540_mfcr, ppc8540_mtcrf, ppc8540_mtjmpr): Add missed
reservation of ppc8540_issue.
From-SVN: r65167
* config/ia64/crti.asm: Clean up trailing whitespace.
Remove trailing hashes (#) from identifiers.
* config/ia64/crtn.asm: Ditto.
* config/ia64/crtend.asm: Remove trailing hashes (#) from
identifiers.
(__do_global_ctors_aux): Align to 32-byte boundary. Add unwind
directives. Drop explicit bundling---it just makes the code
harder to read. Don't save/restore gp needlessly.
* config/ia64/crtbegin.asm: Remove trailing hashes (#) from
identifiers (they're only needed if the identifier would clash
with a register name otherwise).
(__do_global_dtors_aux): Align to 32-byte boundary. Add unwind
directives. Drop explicit bundling---it just makes the code
harder to read.
(__do_jv_register_classes): Ditto.
(.fini_array): Remove "progbits" (newer
assemblers don't like wrong section-types).
(.init_array): Ditto.
From-SVN: r65150
PR fortran/9974
* gcse.c (reg_killed_on_egde): New function to test whether the
given reg is overwritten by any instruction queued on an edge.
(bypass_block): Ignore substitutions killed on incoming edges.
Don't bypass outgoing edges that have queued instructions.
* gcc.c-torture/execute/20030401-1.c: New test case.
From-SVN: r65148
* real.h (EXP_BITS): Make room for...
(struct real_value): ... added canonical bit.
(struct real_format): Added pnan.
(mips_single_format, mips_double_format, mips_extended_format,
mips_quad_format): New.
* real.c: Copy p to pnan in all formats.
(get_canonical_qnan, get_canonical_snan): Set canonical bit.
(real_nan): Use pnan to compute significand's shift.
(real_identical): Disregard significand in canonical
NaNs.
(real_hash): Likewise. Take signalling into account.
(encode_ieee_single, encode_ieee_double, encode_ieee_quad):
Disregard significand bits in canonical NaNs. Set all bits of
canonical NaN if !qnan_msb_set.
(encode_ibm_extended, decode_ibm_extended): Likewise. Use
qnan_msb_set to tell the base double format.
(ibm_extended_format): Use 53 as pnan.
(mips_single_format, mips_double_format, mips_extended_format,
mips_quad_format): Copied from the corresponding ieee/ibm
formats, with qnan_msb_set false.
* config/mips/iris6.h (MIPS_TFMODE_FORMAT): Use mips_extended_format.
* config/mips/linux64.h (MIPS_TFMODE_FORMAT): Use mips_quad_format.
* config/mips/mips.c (override_options): Use mips_single_format
and mips_double_format. Default TFmode to mips_quad_format.
* config/mips/t-linux64 (tp-bit.c): Define QUIET_NAN_NEGATED.
* config/mips/t-irix6: Likewise.
* config/mips/t-mips (fp-bit.c, dp-bit.c): Likewise.
* config/fp-bit.c (pack_d, unpack_d): Obey it.
From-SVN: r65146
2003-04-01 Andrew Pinski <pinskia@physics.uc.edu>
* config-lang.in (gtfiles): add \$(srcdir)/cp/name-lookup.c
after \$(srcdir)/cp/name-lookup.h.
* name-lookup.c: (cxx_binding_make): Use ggc_alloc_clearedinstead
of ggc_alloc. Include gt-cp-name-lookup.h at the end of the file.
* Make-lang.in: (gt-cp-name-lookup.h): is generated by the gtype.
(cp/name-lookup.o): depends on gt-cp-name-lookup.h.
From-SVN: r65142
* gcse.c (struct ls_expr): Added pattern_regs field.
(ldst_entry): Initialize it.
(extract_mentioned_regs, extract_mentioned_regs_helper): New.
(store_ops_ok): Use regs precomputed by them.
(find_loads, store_killed_in_insn, load_kills_store): Change return
type to bool.
(store_killed_before, store_killed_after): Take position of register
set in account.
(reg_set_info): Store position of the setter.
(gcse_main): Enable store motion.
(mems_conflict_for_gcse_p): Enable load motion of non-symbol mems.
(pre_insert_copy_insn, update_ld_motion_stores, insert_store): Prevent rtl
sharing.
(simple_mem): Enable store motion of non-symbol mems.
(regvec): Type changed.
(LAST_AVAIL_CHECK_FAILURE): New.
(compute_store_table_current_insn): New.
(build_store_vectors): Computation of availability and anticipatability
moved ...
(compute_store_table, find_moveable_store): ... here.
(delete_store): Remove senseless comment.
(store_motion): Reorganize.
From-SVN: r65141
* config/rs6000/{40x.md,603.md,6xx.md,7450.md,7xx.md,mpc.md,
power4.md,rios1.md,rios2.md,rs64.md}: Change mult_compare to
imul_compare. Add lmul_compare.
* config/rs6000/power4.md: Bump some latencies. Model extra cycle
in second pair of dispatch slots. Model stores more accurately.
Tweak multiply model. Add bypasses for CR instructions dependent
on complicated compares.
* config/rs6000/rs6000.md (mulsi3): Name imul_compare patterns.
(muldi3): Add lmul_compare patterns.
* config/rs6000/rs6000.c (rs6000_variable_issue): Move FPLOAD_UX
and FPSTORE_UX to split instructions and add COMPARE,
DELAYED_COMPARE, IMUL_COMPARE, LMUL_COMPARE, IDIV, LDIV.
(rs6000_adjust_cost): Add IMUL_COMPARE and LMUL_COMPARE.
(rs6000_rtx_costs): Separate POWER4 multiply case.
From-SVN: r65135
