An ICE arises here because we call cp_get_callee_fndecl_nofold in a
template, and we've got a CALL_EXPR whose CALL_EXPR_FN is a BASELINK.
This tickles the INDIRECT_TYPE_P assert in cp_get_fndecl_from_callee.
Fixed by turning the assert into a condition and returning NULL_TREE
in that case.
PR c++/94937
* cvt.c (cp_get_fndecl_from_callee): Return NULL_TREE if the function
type is not INDIRECT_TYPE_P.
* decl.c (omp_declare_variant_finalize_one): Call
cp_get_callee_fndecl_nofold instead of looking for the function decl
manually.
* g++.dg/cpp1z/constexpr-if34.C: New test.
* g++.dg/cpp2a/is-constant-evaluated10.C: New test.
Adjust test to avoid failures in ILP32 mode.
gcc/testsuite/ChangeLog:
PR middle-end/92815
* gcc.dg/builtin-object-size-20.c: Adjust to avoid failures in
ILP32 mode.
Until 92104 is fixed, let's sorry rather than crash.
PR c++/90915
* parser.c (cp_parser_has_attribute_expression): Sorry on a
type-dependent argument.
* g++.dg/ext/builtin-has-attribute.C: New test.
gcc/testsuite/ChangeLog:
PR middle-end/94940
* gcc.dg/Warray-bounds-61.c: New test.
gcc/ChangeLog:
PR middle-end/94940
* tree-vrp.c (vrp_prop::check_mem_ref): Remove unreachable code.
* tree.c (component_ref_size): Correct the handling or array members
of unions.
Drop a pointless test.
Rename a local variable.
This patch resolves DR 1512 (and, by turn, DR 583). This entails:
1) Relational pointer comparisons against null pointer constants have
been made ill-formed:
void f(char *p) {
if (p > 0)
// ...
}
was always invalid in C but was -- accidentally -- allowed in C++.
2) This was ill-formed:
bool foo(int** x, const int** y) {
return x < y;
}
because 'int**' couldn't be converted to 'const int**'. This was
fixed by re-defining a generic composite pointer type. The composite
type of these two pointers will be 'const int *const *', to which
both pointers can be converted.
3) The overload descriptions for built-in operators were adjusted,
because objects of type std::nullptr_t cannot be used with relational
operators any more.
I fixed 1) by adjusting cp_build_binary_op; we already had a warning
for it so made it a hard error now.
Then 2) required tweaking composite_pointer_type_r. [expr.type] defines
the composite pointer type by using the "cv-combined type." We didn't
implement the [conv.qual]/3.3 part; previously the composite type of
'int**' and 'const int**' was 'const int**', so this didn't compile:
void f(const int **p, int **q) {
true ? p : q;
}
I wrote a more extensive test for this which uses decltype and some
template magic to check the composite type, see composite-ptr-type.C.
We still don't handle everything that [expr.type] requires us to,
but it's pretty close.
And finally 3) was handled in add_builtin_candidate. Turned out we
weren't creating built-in operator candidates when the type was
std::nullptr_t at all. We should, for == and !=. Tested in builtin4.C.
In passing, I'm fixing some of the comments too.
DR 1512
PR c++/87699
* call.c (add_builtin_candidate) <case EQ_EXPR>: Create candidate
operator functions when type is std::nullptr_t for ==/!=.
* typeck.c (composite_pointer_type_r): Add bool a * parameter. Use it
to maybe add "const" to the pointer type.
(composite_pointer_type): Update the call to composite_pointer_type_r.
(cp_build_binary_op): Turn two warning_at into error_at. Print the
types.
* g++.dg/cpp0x/constexpr-array-ptr10.C: Change dg-warning to dg-error
and adjust the expected messages in dg-error.
* g++.dg/expr/composite-ptr-type.C: New test.
* g++.dg/expr/ptr-comp1.C: New test.
* g++.dg/expr/ptr-comp2.C: New test.
* g++.dg/expr/ptr-comp3.C: New test.
* g++.dg/overload/builtin4.C: New test.
* g++.dg/warn/Wextra-3.C: Change dg-warning to dg-error.
In a couple of places in build_over_call we were calling
cp_stabilize_reference but only using the result once, so it isn't needed.
gcc/cp/ChangeLog
2020-05-18 Jason Merrill <jason@redhat.com>
* call.c (build_over_call): Remove unnecessary
cp_stabilize_reference.
This feels extremely obscure but at least it's an opportunity to fix the
comments. P0002R1 removed deprecated operator++(bool) in C++17 so let's
avoid adding a builtin overload candidate for ++ when the type is bool.
* call.c (add_builtin_candidate): Don't create a builtin overload
candidate for ++ when type is bool in C++17.
* g++.dg/overload/builtin5.C: New test.
Current cfns.h includes register-qualified variables and that wouldn't
play well when bootstrapping with GCC that uses the C++17 dialect,
because 'register' was removed in C++17. Regenerating it using the
command specified in cfns.h luckily cleaned this up.
* cfns.h: Regenerated.
We're getting an error when running this test on PowerPC VxWorks 7,
due to an unexpected warning:
| Excess errors:
| cc1: warning: '-mvsx' and '-mno-altivec' are incompatible
The warning comes from a combination of factors:
- The test itself uses -mvsx explicitly via the following directive:
// { dg-options "-O1 -mvsx" }
- Our toolchain was configured so as to make -mno-altivec
the default;
- These two options are mutually exclusive.
This commit adds a powerpc_vsx_ok dg-require-effective-target directive
to that test, and thus making it UNSUPPORTED instead.
Tested on PowerPC VxWorks 7. Also tested on PowerPC ELF as well,
a platform where we do not make -mno-altivec the default, to verify
that the test continues to run as usual in that case.
gcc/testsuite/
* gcc.target/powerpc/pr71763.c: Require powerpc_vsx_ok.
There was general agreement last November that we would move to allowing
C++11 features to be used in GCC 11; this patch implements that direction.
ChangeLog
2020-05-18 Jason Merrill <jason@redhat.com>
* configure.ac: Update bootstrap dialect to -std=c++11.
config/ChangeLog
2020-05-18 Jason Merrill <jason@redhat.com>
* ax_cxx_compile_stdcxx.m4: Import from autoconf archive with
an adjustment to try the default mode.
gcc/ChangeLog
2020-05-18 Jason Merrill <jason@redhat.com>
* aclocal.m4: Add ax_cxx_compile_stdcxx.m4.
* configure.ac: Use AX_CXX_COMPILE_STDCXX(11).
Partially revert the fix for PR93499. Replace by checks for valid
expressions in the declaration of array shape and PDT KIND and LEN
expressions at a later stage.
gcc/fortran/
2020-05-18 Harald Anlauf <anlauf@gmx.de>
PR fortran/95053
* arith.c (gfc_divide): Revert hunk introduced by patch for
PR93499.
* decl.c (variable_decl): Generate error for array shape not being
an INTEGER constant.
(gfc_get_pdt_instance): Generate error if KIND or LEN expressions
in declaration of a PDT instance do not simplify to INTEGER
constants.
gcc/testsuite/
2020-05-18 Harald Anlauf <anlauf@gmx.de>
PR fortran/95053
* gfortran.dg/dec_structure_23.f90: Adjust to new error messages.
* gfortran.dg/pr93499.f90: Adjust to new error messages.
* gfortran.dg/pr95053_2.f90: New test.
* gfortran.dg/pr95053_3.f90: New test.
While bootstrapping GCC on S/390 with --enable-checking=release several
warnings about use of uninitialized variables bitpos, bitregion_start, and
bitregion_end of function pass_store_merging::process_store are raised.
According to PR94952 these seem to be false positives which are silenced by
initialising the mentioned variables.
Bootstrapped on S/390. Ok for master and releases/gcc-10 assuming that
regtest succeeds (still running but I don't see a reason why it
should fail)?
gcc/ChangeLog:
2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
PR tree-optimization/94952
* gimple-ssa-store-merging.c (pass_store_merging::process_store):
Initialize variables bitpos, bitregion_start, and bitregion_end in
order to silence warnings about use of uninitialized variables.
gcc/ChangeLog
2020-04-30 Carl Love <cel@us.ibm.com>
PR target/94833
* config/rs6000/vsx.md (define_expand): Fix instruction generation for
first_match_index_<mode>.
* testsuite/gcc.target/powerpc/builtins-8-p9-runnable.c (main): Add
additional test cases with zero vector elements.
This fixes a bug in the arm backend where GCC generates invalid LDRD
instructions. The LDRD instruction requires the first transfer register to be
even, but GCC attempts to use odd registers here. For example, with the
following C code:
struct c {
double a;
} __attribute((aligned)) __attribute((packed));
struct c d;
struct c f(struct c);
void e() { f(d); }
The struct d is passed in registers r1 and r2 to the function f, and GCC
attempted to do this with a LDRD instruction when compiling with -march=armv7-a
on a soft float toolchain.
The fix is analogous to the corresponding one for STRD in the same function:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=52057dc4ac5295caebf83147f688d769c93cbc8d
2020-05-18 Alex Coplan <alex.coplan@arm.com>
gcc/:
* config/arm/arm.c (output_move_double): Fix codegen when loading into
a register pair with an odd base register.
gcc/testsuite/:
* gcc.c-torture/compile/packed-aligned-1.c: New test.
* gcc.c-torture/execute/packed-aligned.c: New test.
gcc/ChangeLog:
2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.c (ix86_expand_fp_absneg_operator):
Do not emit FLAGS_REG clobber for TFmode.
* config/i386/i386.md (*<code>tf2_1): Rewrite as
define_insn_and_split. Mark operands 1 and 2 commutative.
(*nabstf2_1): Ditto.
(absneg SSE splitter): Use MODEF mode iterator instead of SSEMODEF.
Do not swap memory operands. Simplify RTX generation.
(neg abs SSE splitter): Ditto.
* config/i386/sse.md (*<code><mode>2): Mark operands 1 and 2
commutative. Do not swap operands. Simplify RTX generation.
(*nabs<mode>2): Ditto.
This adjusts the way we compute the stmt insert location for
invariants in BB vectorization context to deal with eventually
sharing invariant SLP nodes for multiple uses. We can no longer
use a single use stmt location then but there's a simple way out.
2020-05-18 Richard Biener <rguenther@suse.de>
* tree-vect-slp.c (vect_slp_bb): Start after labels.
(vect_get_constant_vectors): Really place init stmt after scalar defs.
* tree-vect-stmts.c (vect_init_vector_1): Insert before
region begin.
Add cpu model numbers for Intel Airmont, Tremont, Comet Lake, Ice Lake
and Tiger Lake processor families.
* config/i386/driver-i386.c (host_detect_local_cpu): Support
Intel Airmont, Tremont, Comet Lake, Ice Lake and Tiger Lake
processor families.
This fixes always-inlining across -fnon-call-exception boundaries
for conditions which we do not allow to throw.
2020-05-18 Richard Biener <rguenther@suse.de>
PR middle-end/95171
* tree-inline.c (remap_gimple_stmt): Split out trapping compares
when inlining into a non-call EH function.
* gcc.dg/pr95171.c: New testcase.
The following testcase shows a missed optimization that then leads to
wrong-code when issueing SMed stores on exits. When we were able to
compute an ordered sequence of stores for an exit we need to emit
that in the correct order and we can emit it disregarding to any
conditional for whether a store actually happened (we know it did).
We can also improve detection as of whether we need conditional
processing at all. Both parts fix the testcase.
2020-05-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/95172
* tree-ssa-loop-im.c (execute_sm): Get flag whether we
eventually need the conditional processing.
(execute_sm_exit): When processing an orderd sequence
avoid doing any conditional processing.
(hoist_memory_references): Pass down whether all edges
have ordered processing for a ref to execute_sm.
* gcc.dg/torture/pr95172.c: New testcase.
This avoids a (bogus) warning that occurs with some bootstrap
compilers.
gcc/cp/ChangeLog:
2020-05-17 Iain Sandoe <iain@sandoe.co.uk>
* coroutines.cc (morph_fn_to_coro): Initialize the
gro variable.
* config/h8300/predicates.md (pc_or_label_operand): New predicate.
* config/h8300/jumpcall.md (branch_true, branch_false): Consolidate
into a single pattern using pc_or_label_operand.
* config/h8300/combiner.md (bit branch patterns): Likewise.
* config/h8300/peepholes.md (HImode and SImode branches): Likewise.
Add V1TI vector register push and split it after reload to a sequence
of:
(set (reg:P SP_REG) (plus:P SP_REG) (const_int -8)))
(set (match_dup 0) (match_dup 1))
so that STV pass can convert TI mode integer push to V1TI vector register
push. Rename has_non_address_hard_reg to pseudo_reg_set, combine calls
of single_set and has_non_address_hard_reg to pseudo_reg_set, to ignore
pseudo register push.
Remove c-c++-common/dfp/func-vararg-mixed-2.c since it is compiled with
-mpreferred-stack-boundary=2 and leads to segfault:
Dump of assembler code for function __bid_nesd2:
0x08049210 <+0>: endbr32
0x08049214 <+4>: push %esi
0x08049215 <+5>: push %ebx
0x08049216 <+6>: call 0x8049130 <__x86.get_pc_thunk.bx>
0x0804921b <+11>: add $0x8de5,%ebx
0x08049221 <+17>: sub $0x20,%esp
0x08049224 <+20>: mov 0x30(%esp),%esi
0x08049228 <+24>: pushl 0x2c(%esp)
0x0804922c <+28>: call 0x804e600 <__bid32_to_bid64>
0x08049231 <+33>: mov %esi,(%esp)
0x08049234 <+36>: movd %edx,%xmm1
0x08049238 <+40>: movd %eax,%xmm0
0x0804923c <+44>: punpckldq %xmm1,%xmm0
=> 0x08049240 <+48>: movaps %xmm0,0x10(%esp)
0x08049245 <+53>: call 0x804e600 <__bid32_to_bid64>
0x0804924a <+58>: push %edx
0x0804924b <+59>: push %eax
0x0804924c <+60>: pushl 0x1c(%esp)
0x08049250 <+64>: pushl 0x1c(%esp)
0x08049254 <+68>: call 0x804b260 <__bid64_quiet_not_equal>
0x08049259 <+73>: add $0x34,%esp
0x0804925c <+76>: pop %ebx
0x0804925d <+77>: pop %esi
0x0804925e <+78>: ret
when libgcc is compiled with -msse2. According to GCC manual:
'-mpreferred-stack-boundary=NUM'
Attempt to keep the stack boundary aligned to a 2 raised to NUM
byte boundary. If '-mpreferred-stack-boundary' is not specified,
the default is 4 (16 bytes or 128-bits).
*Warning:* If you use this switch, then you must build all modules
with the same value, including any libraries. This includes the
system libraries and startup modules.
c-c++-common/dfp/func-vararg-mixed-2.c, which was added by
commit 3b2488ca6ece182f2136a20ee5fa0bb92f935b0f
Author: H.J. Lu <hongjiu.lu@intel.com>
Date: Wed Jul 30 19:24:02 2008 +0000
func-vararg-alternate-d128-2.c: New.
2008-07-30 H.J. Lu <hongjiu.lu@intel.com>
Joey Ye <joey.ye@intel.com>
* gcc.dg/dfp/func-vararg-alternate-d128-2.c: New.
* gcc.dg/dfp/func-vararg-mixed-2.c: Likewise.
isn't expected to work with libgcc.
gcc/
PR target/95021
* config/i386/i386-features.c (has_non_address_hard_reg):
Renamed to ...
(pseudo_reg_set): This. Return the SET expression. Ignore
pseudo register push.
(general_scalar_to_vector_candidate_p): Combine single_set and
has_non_address_hard_reg calls to pseudo_reg_set.
(timode_scalar_to_vector_candidate_p): Likewise.
* config/i386/i386.md (*pushv1ti2): New pattern.
gcc/testsuite/
PR target/95021
* c-c++-common/dfp/func-vararg-mixed-2.c: Removed.
* gcc.target/i386/pr95021-1.c: New test.
* gcc.target/i386/pr95021-2.c: Likewise.
* gcc.target/i386/pr95021-3.c: Likewise.
* gcc.target/i386/pr95021-4.c: Likewise.
* gcc.target/i386/pr95021-5.c: Likewise.
- core.cpuid has been fixed to not use i7 detection on AMD processors.
- std.net.curl has been fixed to correctly handle HTTP/2 status lines.
- std.zip has had a test fixed to not rely on unzip being installed.
Fixes: PR d/95166
PR d/95167
PR d/95168
Reviewed-on: https://github.com/dlang/druntime/pull/3107https://github.com/dlang/phobos/pull/7486
Add a strncmp test for the cmpstrn pattern with neither of the strings
is a constant string. We can expand the cmpstrn pattern to "repz cmpsb"
only if one of the strings is a constant so that expand_builtin_strncmp()
can write the length argument to be the minimum of the const string
length and the actual length argument. Otherwise, "repz cmpsb" may pass
the 0 byte.
* gcc.target/i386/strncmp-1.c: New test.
New class live_names to maintain the set of SSA names live.
Fix whitespace in vrp_insert.
Move a few more methods related to ASSERT_EXPR insertion into vrp_insert.
This is a case where the standard contains conflicting information.
after discussion between implementators, the accepted intent is of
[class.copy.elision]. This amends the handling of co_return statements
to follow that.
gcc/cp/ChangeLog:
2020-05-16 Iain Sandoe <iain@sandoe.co.uk>
* coroutines.cc (finish_co_return_stmt): Implement rules
from [class.copy.elision] /3.
gcc/testsuite/ChangeLog:
2020-05-16 Iain Sandoe <iain@sandoe.co.uk>
* g++.dg/coroutines/co-return-syntax-10-movable.C: New test.
* config/h8300/h8300.md (SFI iterator): New iterator for
SFmode and SImode.
* config/h8300/peepholes.md (memory comparison): Use mode
iterator to consolidate 3 patterns into one.
(stack allocation and stack store): Handle SFmode. Handle
8 byte allocations.
We sometimes fail to reject an invalid non-dependent operand to decltype
when inside a template, because finish_decltype_type resolves the
decltype to the TREE_TYPE of the operand before we ever instantiate and
fully process the operand. Fix this by adding a call to
instantiate_non_dependent_expr_sfinae in finish_decltype_type.
gcc/cp/ChangeLog:
PR c++/57943
* semantics.c (finish_decltype_type): Call
instantiate_non_dependent_expr_sfinae on the expression.
gcc/testsuite/ChangeLog:
PR c++/57943
* g++.dg/cpp0x/decltype76.C: New test.
Now that GCC 10 is out it seems time. People can still choose to disable
coroutines with -fno-coroutines.
This also switches the coroutines testsuite to run in C++20 mode. The
change to coro.h is only necessary for co-await-11-forwarding.C; we could
alternatively #include <utility> just in that file.
gcc/c-family/ChangeLog
2020-05-15 Jason Merrill <jason@redhat.com>
* c-opts.c (set_std_cxx20): Set flag_coroutines.
gcc/testsuite/ChangeLog
2020-05-15 Jason Merrill <jason@redhat.com>
* g++.dg/coroutines/coro.h: Always #include <utility>.
* g++.dg/coroutines/coroutines.exp (DEFAULT_COROFLAGS): Use
-std=c++20.
BU_FUTURE_MISC_2 is (currently) only used for instructions that require
64-bit registers.
2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_2): Also require
RS6000_BTM_POWERPC64.
Tests that use the __int128 type need to use the int128 selector.
2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
gcc/testsuite/
* gcc.target/powerpc/vec-gnb-0.c: Use int128 effective target.
* gcc.target/powerpc/vec-gnb-1.c: Ditto.
* gcc.target/powerpc/vec-gnb-2.c: Ditto.
* gcc.target/powerpc/vec-ternarylogic-8.c: Ditto.
* gcc.target/powerpc/vec-ternarylogic-9.c: Ditto.
* gcc.target/powerpc/vec-ternarylogic-10.c: Ditto.
The powerpc64 effective target unfortunately does not mean the target
has 64-bit instructions enabled (i.e., -mpowerpc64): instead, it means
that the assembler supports it.
Let's use the lp64 effective target instead for these tests.
2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
gcc/testsuite/
* gcc.target/powerpc/cntlzdm-0.c: Use lp64 instead of powerpc64.
* gcc.target/powerpc/cntlzdm-1.c: Ditto.
* gcc.target/powerpc/cnttzdm-1.c: Ditto.
* gcc.target/powerpc/pdep-0.c: Ditto.
* gcc.target/powerpc/pdep-1.c: Ditto.
* gcc.target/powerpc/pextd-0.c: Ditto.
* gcc.target/powerpc/pextd-1.c: Ditto.
The process_init_constructor_array part of my PR90996 patch turns out to
be neither necessary nor sufficient to make the pr90996.C testcase work,
and I wasn't able to come up with a testcase that demonstrates this part
is ever necessary.
gcc/cp/ChangeLog:
Revert:
2020-04-07 Patrick Palka <ppalka@redhat.com>
PR c++/90996
* typeck2.c (process_init_constructor_array): Propagate
CONSTRUCTOR_PLACEHOLDER_BOUNDARY up from each element
initializer to the array initializer.
gcc/testsuite/ChangeLog:
PR c++/90996
* g++.dg/cpp1y/pr90996.C: Turn into execution test to verify
that each PLACEHOLDER_EXPR gets correctly resolved.
