* config/m68k/m68k.h (CONDITIONAL_REGISTER_USAGE): If we have no
68881, we have no 68881 registers at all.
(HARD_REGNO_MODE_OK): It is always OK to put a MODE_FLOAT
value in a 68881 register if it is available.
From-SVN: r30861
* config/sparc/sparc.c (fp_sethi_p, fp_mov_p, fp_high_losum_p):
New functions.
* config/sparc/sparc-protos.h: Add them.
* config/sparc/sparc.h: Add them to PREDICATE_CODES.
(EXTRA_CONSTRAINT_BASE): New macro, handling Q, R, and S
constraints which use those helpers.
(EXTRA_CONSTRAINT): Use this new macro.
* md.texi: Update sparc target constraints documentation.
* config/sparc/sparc.md (clear_sf, clear_sfp, movsf_const_intreg,
movsf_const_high, movsf_const_lo, movsf_insn): Delete.
(movsf_insn_novis_liveg0, movsf_insn_novis_noliveg0,
movsf_insn_vis, movsf_lo_sum, movsf_high): New patterns.
(movsf high/lo_sum split): Rework for new patterns.
(movsf expander): Allow storing fp_zero to memory if ! live_g0.
From-SVN: r30857
* regclass.c (globalize_reg): Re-instate test that allows
fixed registers to be declared as a variable even after functions
are defined.
* testsuite/gcc.dg/991209-1.c: New test.
From-SVN: r30853
* i386.md (cpu attribute): Add "athlon".
(athlon_decode): New attribute.
(Athlon scheduling units definitions): New.
(fcmp and shld patterns): Set athlon_decode to "vector".
* i386.c (athlon_cost): New.
(m_ATHLON): New.
(x86_use_leave, x86_push_memory, x86_movx, x86_cmove, x86_deep_branch,
x86_use_sahf): Set for Athlon.
(x86_use_fiop): Unset for Athlon.
(override_options): Define Athlon alignments and "athlon" name.
(x86_adjust_cost): Penalize AGI and delayed latencies for Athlon.
* i386.h (TARGET_ATHLON): New.
(enum processor_type): Add PROCESSOR_ATHLON.
(TARGET_CPU_DEFAULT_SPEC): Set to "-D__tune_athlon__"
for CPU_DEFAULT==6
(TARGET_CPP_CPU_SPECS): Set -D__tune_athlon__ for Athlon.
From-SVN: r30852
* except.c (expand_throw): Add static attribute to match
prototype.
* Makefile.in (semantics.o): Add dependency on output.h.
* semantics.c: Include output.h for declaration of
make_function_rtl.
From-SVN: r30850
* decl.c (init_decl_processing): Reenable inlining on trees.
(finish_function): Likewise.
* expr.c (cplus_expand_expr): Don't handle AGGR_INIT_EXPR here.
* semantics.c (simplify_aggr_init_exprs): New function.
(expand_body): Use it.
* tree.c (walk_tree): Special-case TARGET_EXPRs since they
sometimes present the same sub-tree twice.
From-SVN: r30849
* config/sparc/sparc.h (PROMOTE_FOR_CALL_ONLY): Define.
* calls.c (precompute_arguments): Make sure initial_value contains
value pseudo which CSE expects.
* cse.c (struct set): New entry orig_src.
(cse_insn): Set it early on entry, use it for libcall EQUIV note
replacement.
From-SVN: r30846
> * decl.c (init_decl_processing): Mark throw_node as a noreturn
> function with side effects.
> (init_decl_processing): Mark all memory allocating DECLs with
> DECL_IS_MALLOC.
From-SVN: r30845
* config/sparc/linux64.h (TARGET_DEFAULT): Make -mapp-regs
default on linux64 again.
* config/sparc/t-linux64: Add mno-app-regs and non-medlow code
models for multilibing.
* genmultilib: Accept | as alternative separator within a set in
MULTILIB_OPTIONS.
From-SVN: r30841
* longlong.h: Merge in changes from glibc.
Also don't clobber %g2 register in 32bit SPARC assembly, so that
-mno-app-regs libgcc can be compiled.
* libgcc2.c: Add defines so that the updated longlong.h
can be used in libgcc2.a. Also, make sure on most architectures
(at least on all which have optimized code in longlong.h defined
for) {SI,W}_TYPE_SIZE is suitable for preprocessor tests.
From-SVN: r30836
* config/sparc/sol2-64.h: Same as sol2-sld-64.h, except that
`-m EMULATION' is added to non-default LINK_ARCH_SPECs.
* configure.in: Use sol2-64.h instead of sol2-sld-64.h if linker
is GNU ld.
* configure: Rebuilt.
From-SVN: r30830
* Makefile.in (FPBIT_FUNCS, DPBIT_FUNCS): Add _sf_to_usi
_df_to_usi. Required by some targets, so US_SOFTWARE_GOFAST calls to
functions like dptoul will be resolved.
(libgcc2.a): Make sure that the object files from DPBIT are named
differently (prefix `_dp') from those that would be coming from
FPBIT.
From-SVN: r30828
* configure.in: When target is sparc* and tm_file contains 64,
test for 64bit support in assembler. If not supported, remove
sparc/t-sol2-64 from target-dependent Makefile fragments.
(AS_SPARC64_FLAG): Define to the assembler flag for 64bit.
(HAVE_AS_OFFSETABLE_LO10): Rework test to use these flags.
(HAVE_AS_REGISTER_PSEUDO_OP): Use config.cache.
* acconfig.h (AS_SPARC64_FLAG): Added.
* configure, config.in: Rebuilt.
* config/sparc/sol2-sld-64.h: Same as sol2.h, if without 64bit
support. Use AS_SPARC64_FLAG.
From-SVN: r30827
* configure.in (sparc64-*-linux*): Use posix threads if enabled.
* configure: Rebuilt.
* config/sparc/linux64.h: Default to -mcpu=ultrasparc if no
-mcpu is given and we're doing 64bit compiles.
From-SVN: r30825
* config/sparc/sparc.c (hard_32bit_mode_classes): Mark registers
suitable for holding OFmode values so that gcc works with complex
quad long doubles.
(hard_64bit_mode_classes): Likewise.
From-SVN: r30821
* loop.h (struct induction): Add multi_insn_incr.
* loop.c (basic_induction_var): New multi_insn_incr argument.
Set it if we search back through previous insns for the biv.
(record_biv): New multi_insn_incr argument; fill in struct induction.
(strength_reduce): Discard an iv with multiple bivs, any of
which require multiple insns to increment.
From-SVN: r30820
