PR libstdc++/80034
* include/bits/list.tcc (merge(list&&)): Use const for the size_t
in the catch-block.
(merge(list&&, _StrictWeakOrdering)): Likewise.
* testsuite/23_containers/list/operations/80034.cc: New.
From-SVN: r246107
While integrating the d_printing recursion guard change into gdb I
noticed we forgot to initialize the demangle_component d_printing
field in cplus_demangle_fill_{name,extended_operator,ctor,dtor}.
As is done in cplus_demangle_fill_{component,builtin_type,operator}.
It happened to work because in gcc all demangle_components were
allocated through d_make_empty. But gdb has its own allocation
mechanism (as might other users).
libiberty/ChangeLog:
* cp-demangle.c (cplus_demangle_fill_name): Initialize
demangle_component d_printing.
(cplus_demangle_fill_extended_operator): Likewise.
(cplus_demangle_fill_ctor): Likewise.
(cplus_demangle_fill_dtor): Likewise.
From-SVN: r246105
2017-03-13 Martin Liska <mliska@suse.cz>
PR middle-end/78339
* ipa-pure-const.c (warn_function_noreturn): If the declarations
is a CHKP clone, use original declaration.
2017-03-13 Martin Liska <mliska@suse.cz>
PR middle-end/78339
* gcc.target/i386/mpx/pr78339.c: New test.
From-SVN: r246098
gcc/
2017-03-13 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_init): Use multiplier whenever we have it.
(arc_conditional_register_usage): Use a different allocation order
when optimizing for size.
* common/config/arc/arc-common.c (arc_option_optimization_table):
Section anchors default on when optimizing for size.
From-SVN: r246091
Move pattern (movsi_insn) allows predicated instructions to be
instructions which can hold all registers. However, the conditional
variant doesn't. This patch fixes this problem.
2017-03-13 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (movsi_cond_exec): Update constraint.
From-SVN: r246088
fwprop step is placing in the REG_EQUIV notes constant pic unspecs
expressions. Then, loop may use these notes for optimizations
rezulting in complex patterns that are not supported by the current
implementation.
The patch adds handling of complex PIC addresses having MINUS or UNARY
operations.
gcc/
2017-03-13 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_legitimize_pic_address): Handle PIC
expressions with MINUS and UNARY ops.
gcc/testsuite
2017-03-13 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/pr9001090948.c: New file.
From-SVN: r246087
check_effective_target_broken_cplxf_arg is buggy. It actually tests
if passing complex float works, not if it fails. Also, it only runs
the test for target powerpc64-linux, but we are biarch, so it should
be powerpc*-linux.
This also changes the early-out conditions to be separate, because
the big combined condition was hard to follow.
This fixes the libstdc++ tests:
Running target unix/-m64
XPASS: 26_numerics/complex/13450.cc execution test
XPASS: 26_numerics/complex/pow.cc execution test
XPASS: 26_numerics/complex/value_operations/1.cc execution test
which were the last failing libstdc++ tests on BE.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_broken_cplxf_arg):
Fix test. Make early-out condition return early. Correct comments.
From-SVN: r246072
2017-03-11 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR libgfortran/78854
* io/list_read.c (nml_get_obj_data): Stash internal unit for
later use by child procedures.
* io/write.c (nml_write_obj): Likewise.
* io/tranfer.c (data_transfer_init): Minor whitespace.
* io/unit.c (set_internal_uit): Look for the stashed internal
unit and use it if found.
* gfortran.dg/dtio_25.f90: New test.
From-SVN: r246070
gcc/ChangeLog:
PR translation/79923
* auto-profile.c (get_combined_location): Convert leading
character of diagnostics to lower case and remove trailing period.
(read_profile): Likewise for various diagnostics.
* config/arm/arm.c (arm_option_override): Remove trailing period
from various diagnostics.
* config/msp430/msp430.c (msp430_expand_delay_cycles): Likewise.
(msp430_expand_delay_cycles): Likewise.
From-SVN: r246067
gcc/ChangeLog:
PR target/79925
* config/aarch64/aarch64.c (aarch64_validate_mcpu): Quote the
full command-line argument, rather than just "str".
(aarch64_validate_march): Likewise.
(aarch64_validate_mtune): Likewise.
From-SVN: r246066
PR rtl-optimization/78911
* lra-assigns.c (must_not_spill_p): New function.
(spill_for): Use it.
PR rtl-optimization/78911
* gcc.target/i386/pr78911-1.c: New test.
* gcc.target/i386/pr78911-2.c: New test.
From-SVN: r246059
These files won't build on targets that do not have AltiVec enabled,
breaking the build, unless we tell GAS that Altivec insns are fine.
The alternative is to not build these files in that case, which is much
more complicated.
libgcc/
* config/rs6000/crtrestvr.s: Use .machine altivec.
* config/rs6000/crtsavevr.s: Ditto.
From-SVN: r246051
gcc/c-family/ChangeLog:
PR c/79921
* c-indentation.c (warn_for_misleading_indentation): Remove parens
from inform's message, so that xgettext can locate it.
From-SVN: r246045
gcc/ChangeLog:
PR bootstrap/79952
* read-rtl-function.c (function_reader::read_rtx_operand): Update
x with result of extra_parsing_for_operand_code_0.
(function_reader::extra_parsing_for_operand_code_0): Convert
return type from void to rtx, returning x. When reading
SYMBOL_REF with SYMBOL_FLAG_HAS_BLOCK_INFO, reallocate x to the
larger size containing struct block_symbol.
From-SVN: r246044
This fixes float128 on BE and on 32-bit.
The configure tests need to use -mabi=altivec for 32-bit, since it is
not the default there. That also enables the "vector" keyword, used by
the tests. To do this it temporarily adds a few flags to the CFLAGS
variable.
It also fixes a syntax error in the libgcc_cv_powerpc_float128_hw test
(the function name was missing in the function declaration).
Regenerating config.in (via autoreconf) removed the duplicate definition
of HAVE_SOLARIS_CRTS.
Finally, this adds a "-mfloat128-hardware requires -m64" test to
rs6000.c: all the current patterns need 64-bit registers. Maybe we'll
want to add float128 hardware support to 32-bit some day, but certainly
not today.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Disallow
-mfloat128-hardware without -m64.
libgcc/
* configure.ac (test for libgcc_cv_powerpc_float128): Temporarily
modify CFLAGS. Add -mabi=altivec -mvsx -mfloat128.
(test for libgcc_cv_powerpc_float128_hw): Add -mpower9-vector and
-mfloat128-hardware to the CFLAGS. Fix syntax error in the C snippet.
* configure: Regenerate.
* config.in: Regenerate.
From-SVN: r246043
gcc:
2017-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
PR target/79941
* config/rs6000/rs6000.c (builtin_function_type): Add VMUL*U[HB]
entries to the case statement that marks unsigned arguments to
overloaded functions.
testsuite:
2017-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
PR target/79941
* gcc.target/powerpc/fold-vec-mult-even_odd_misc.c: New test.
* gcc.target/powerpc/fold-vec-mult-even_odd_char.c: New test.
* gcc.target/powerpc/fold-vec-mult-even_odd_short.c: New test.
From-SVN: r246040
