This patch fixes PR c++/96437 which is an ICE-on-invalid-code regression
affecting mainline.
2022-03-08 Roger Sayle <roger@nextmovesoftware.com>
gcc/cp/ChangeLog
PR c++/96437
* parser.cc (synthesize_implicit_template_parm): Check that
TREE_VALUE (new_parm) isn't error_mark_node before setting its
DECL_VIRTUAL_P.
gcc/testsuite/ChangeLog
PR c++/96437
* g++.dg/cpp2a/pr96437.C: New test case.
This patch fixes PR c++/96329 which is an ICE-on-invalid-code regression
affecting mainline.
2022-03-08 Roger Sayle <roger@nextmovesoftware.com>
gcc/cp/ChangeLog
PR c++/96329
* parser.cc (cp_parser_linkage_specification): Treat the case where
linkage is error_mark_node as "invalid linkage-specification".
gcc/testsuite/ChangeLog
PR c++/96329
* g++.dg/template/pr96329.C: New test case.
In r10-6329 I tried to optimize the number of calls to v_d_e_p in
convert_nontype_argument by remembering whether the expression was
value-dependent in a bool flag. I did that wrongly assuming that its
value-dependence will not be changed by build_converted_constant_expr.
This testcase shows that it can: b_c_c_e gets a VAR_DECL for m_parameter,
which is not value-dependent, but we're converting it to "const int &"
so it returns
(const int &)(const int *) &m_parameter
which suddenly becomes value-dependent because of the added ADDR_EXPR:
has_value_dependent_address is now true because m_parameter's context S<T>
is dependent. With this bug in place, we went to the second branch here:
if (TYPE_REF_OBJ_P (TREE_TYPE (expr)) && val_dep_p)
/* OK, dependent reference. We don't want to ask whether a DECL is
itself value-dependent, since what we want here is its address. */;
else
{
expr = build_address (expr);
if (invalid_tparm_referent_p (type, expr, complain))
return NULL_TREE;
}
wherein build_address created a bad tree and then i_t_r_p complained.
PR c++/104108
gcc/cp/ChangeLog:
* pt.cc (convert_nontype_argument): Recompute
value_dependent_expression_p after build_converted_constant_expr.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/alias-decl-74.C: New test.
This change ensures that we never output a result name in the export
data if there is only a single result. Previously we would output a ?
if the single result had a name. That made the output unstable,
because the hashing ignores the result name, so whether we output a ?
or not depended on how equal hash elements were handled.
For https://gcc.gnu.org/PR104832
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/390874
Attributes deprecated and unavailable are largely the same, except
that the former produces a warning whereas the latter produces an error.
So is_late_template_attribute should treat them the same. Confirmed by
Iain that this divergence is not intentional:
<https://gcc.gnu.org/pipermail/gcc-patches/2022-February/591007.html>.
gcc/cp/ChangeLog:
* decl2.cc (is_late_template_attribute): Do not defer attribute
unavailable.
* pt.cc (tsubst_enum): Set TREE_UNAVAILABLE.
gcc/testsuite/ChangeLog:
* g++.dg/ext/attr-unavailable-9.C: Add dg-error.
gcc/fortran/ChangeLog:
PR fortran/104811
* frontend-passes.cc (optimize_minmaxloc): Do not attempt
frontend-optimization of MINLOC/MAXLOC for character arrays, as
there is no suitable code yet for inline expansion.
gcc/testsuite/ChangeLog:
PR fortran/104811
* gfortran.dg/minmaxloc_16.f90: New test.
On the following testcase, we emit "did you mean '__dt '?" in the error
message. "__dt " shows there because it is dtor_identifier, but we
shouldn't suggest those to the user, they are purely internal and can't
be really typed by the user because of the final space in it.
2022-03-08 Jakub Jelinek <jakub@redhat.com>
PR c++/104806
* search.cc (lookup_field_fuzzy_info::fuzzy_lookup_field): Ignore
identifiers with space at the end.
* g++.dg/spellcheck-pr104806.C: New test.
Commits r12-7342 and r12-7344 made some cleanup, leaving
arm_binop_none_none_unone_qualifiers unused.
This is causing build failures with -Werror (eg bootstrap).
This patch fixes the problem by removing the definition of
arm_binop_none_none_unone_qualifiers and
BINOP_NONE_NONE_UNONE_QUALIFIERS which are now unused.
Tested by bootstraping on arm-linux-gnueaibhf.
2022-03-04 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/arm-builtins.cc
(arm_binop_none_none_unone_qualifiers): Delete.
(BINOP_NONE_NONE_UNONE_QUALIFIERS): Delete.
This amends an error message to correct punctuation and a little
better wording.
Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
PR translation/104552
gcc/ChangeLog:
* config/host-darwin.cc (darwin_gt_pch_get_address): Amend
the PCH out of memory error message punctuation and wording.
In r270550, Jakub fixed classify_insn to handle asm goto: if the asm can
jump to a label, the insn should be a JUMP_INSN.
However, as the following testcase shows, non-null ASM_OPERANDS_LABEL_VEC
doesn't guarantee that the rtx has any actual labels it can branch to.
Here, the rtvec has 0 elements because expand_asm_stmt created it:
rtvec labelvec = rtvec_alloc (nlabels); // nlabels == 0
This causes an ICE in update_br_prob_note: BRANCH_EDGE (bb) crashes
because there's no branch edge. I think we can fix this by checking
that there is at least one label the asm can jump to before wrapping
the ASM_OPERANDS in a JUMP_INSN.
PR rtl-optimization/104777
gcc/ChangeLog:
* rtl.cc (classify_insn): For ASM_OPERANDS, return JUMP_INSN only if
ASM_OPERANDS_LABEL_VEC has at least one element.
gcc/testsuite/ChangeLog:
* gcc.dg/torture/tls/pr104777.c: New test.
Disallow stack realignment and regparm nested function with EH return
since they don't work together.
gcc/
PR target/104781
* config/i386/i386.cc (ix86_expand_epilogue): Sorry if there is
stack realignment or regparm nested function with EH return.
gcc/testsuite/
PR target/104781
* gcc.target/i386/eh_return-1.c: Add -mincoming-stack-boundary=4.
* gcc.target/i386/eh_return-2.c: Likewise.
This patch relaxes the addressing modes for the mve full load and stores (by
full loads and stores I mean non-widening or narrowing loads and stores resp).
The code before was requiring a LO_REGNUM for these, where this is only a
requirement if the load is widening or the store narrowing.
gcc/ChangeLog:
PR target/104790
* config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.
* config/arm/arm.cc (mve_vector_mem_operand): Relax constraint on base
register for non widening loads or narrowing stores.
POSIX expr does not support the 'match' keyword, so the git-descr.sh
scripts should use ':' instead.
contrib/ChangeLog:
PR other/102664
* git-descr.sh: Use portable form of expr match.
This adds a --param to allow disabling of vectorization of
floating point inductions. Ontop of -Ofast this should allow
549.fotonik3d_r to not miscompare.
2022-03-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/84201
* params.opt (-param=vect-induction-float): Add.
* doc/invoke.texi (vect-induction-float): Document.
* tree-vect-loop.cc (vectorizable_induction): Honor
param_vect_induction_float.
* gcc.dg/vect/pr84201.c: New testcase.
This file has the SGI copyright notice, but contains no code from
the SGI STL. It was entirely written by me in 2019, originally as part
of the <memory> header. When I extracted it into a new header I
accidentally copied across the SGI copyright, but that only applies to
some much older parts of <memory>.
libstdc++-v3/ChangeLog:
* include/bits/uses_allocator_args.h: Remove incorrect copyright
notice.
These testcases declare requiring vect_int which sparc declares as well however
sparc doesn't have an optab to vectorize comparisons so these testcases fail to
vectorize and so the tests fail.
As such best coure of action is to just skip them on sparc as comparisons are
somewhat expected from a target that can do SIMD.
gcc/testsuite/ChangeLog:
PR tree-optimization/104755
* gcc.dg/vect/vect-bic-bitmask-10.c: Disable sparc.
* gcc.dg/vect/vect-bic-bitmask-11.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-12.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-2.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-23.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-3.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-4.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-5.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-6.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-8.c: Likewise.
* gcc.dg/vect/vect-bic-bitmask-9.c: Likewise.
One of the mistakes reported in PR 104552 is repeated "that" in
description of ipa-cp-recursive-freq-factor which I introduced. This
patch removes one of them.
gcc/ChangeLog:
2022-03-07 Martin Jambor <mjambor@suse.cz>
PR translation/104552
* params.opt (ipa-cp-recursive-freq-factor): Remove repeated word
"that" in the description.
The following makes sure to guard the modref query in VN on a
pointer typed argument.
2022-03-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/104825
* tree-ssa-sccvn.cc (visit_reference_op_call): Properly
guard modref get_ao_ref on a pointer typed argument.
* gcc.dg/torture/pr104825.c: New testcase.
Other callers of mark_single_function might also want to look through these
wrapapers.
PR c++/104618
gcc/cp/ChangeLog:
* decl2.cc (mark_single_function): Look through parens and location
wrapper.
* typeck.cc (cp_build_addr_expr_1): Not here.
PR analyzer/101983 reports what I thought were false positives
from -Wanalyzer-malloc-leak, but on closer inspection, the
analyzer is correctly reporting heap-allocated buffers that are
no longer reachable.
However, these "leaks" occur at the end of "main". The analyzer already
has some logic to avoid reporting leaks at the end of main, where the
leak is detected at the end of the EXIT basic block. However, in this case,
the leak is detected at the clobber in BB 2 here:
<bb 2> :
func (&res);
res ={v} {CLOBBER(eol)};
_4 = 0;
<bb 3> :
<L0>:
return _4;
where we have a chain BB 2 -> BB 3 -> EXIT BB.
This patch generalizes the "are we at the end of 'main'" detection to
handle such cases, silencing -Wanalyzer-malloc-leak on them.
There's a remaining issue where the analyzer unhelpfully describes one
of the leaking values as '<unknown>', rather than 'res.a', but I'm
leaving that for a followup (covered by PR analyzer/99771).
gcc/analyzer/ChangeLog:
PR analyzer/101983
* engine.cc (returning_from_function_p): New.
(impl_region_model_context::on_state_leak): Use it when rejecting
leaks at the return from "main".
gcc/testsuite/ChangeLog:
PR analyzer/101983
* gcc.dg/analyzer/pr101983-main.c: New test.
* gcc.dg/analyzer/pr101983-not-main.c: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
As C++20 has already been published, we don't need to link to the draft
(which is now the C++23 draft anyway). And there's no need to say it's
part of the C++20 spec, or that there might be defect reports. That's
true for everything in C++20, so calling it out here just for Modules
isn't needed.
gcc/ChangeLog:
* doc/invoke.texi (C++ Modules): Remove anachronism.
The _GLIBCXX_PSEUDO_VISIBILITY macro isn't defined until after including
os_defines.h, so we can't use _GLIBCXX_VISIBILITY early in c++config.
Replace the uses of that macro with #pragma visibility push(default)
instead.
libstdc++-v3/ChangeLog:
PR libstdc++/104807
* include/bits/c++config (__terminate, __glibcxx_assert_fail):
Replace _GLIBCXX_VISIBILITY on function with visibility pragma.
(__is_constant_evaluated): Add visibility pragma.
Note -fvar-tracking is enabled automatically with OPT_LEVELS_1_PLUS and
so we need to drop it if we are called from optimize attribute and the
option is unset.
PR middle-end/104381
gcc/ChangeLog:
* opts.cc (finish_options): If debug info is disabled
(debug_info_level) and -fvar-tracking is unset, disable it.
gcc/testsuite/ChangeLog:
* gcc.dg/pr104381.c: New test.
After more than 2 years I've run my
https://gcc.gnu.org/ml/gcc-patches/2017-02/msg00844.html
script again. While it has lots of false positives, it discovered
two bugs.
2022-03-07 Jakub Jelinek <jakub@redhat.com>
gcc/c/
* c-parser.cc (c_parser_omp_clause_map): Add missing space in string
literal.
gcc/cp/
* parser.cc (cp_parser_omp_clause_map): Add missing space in string
literal.
Like in r10-7215-g700d4cb08c88aec37c13e21e63dd61fd698baabc 2 years ago,
I've run
grep -v 'long long\|optab optab\|template template\|double double' *.{[chS],cc} */*.{[chS],cc} *.def config/*/* 2>/dev/null | grep ' \([a-zA-Z]\+\) \1 '
and for the cases that looked clearly wrong changed them, mostly by removing
one of the duplicated words but in some cases with other changes.
2022-03-07 Jakub Jelinek <jakub@redhat.com>
gcc/
* tree-ssa-propagate.cc: Fix up duplicated word issue in a comment.
* config/riscv/riscv.cc: Likewise.
* config/darwin.h: Likewise.
* config/i386/i386.cc: Likewise.
* config/aarch64/thunderx3t110.md: Likewise.
* config/aarch64/fractional-cost.h: Likewise.
* config/vax/vax.cc: Likewise.
* config/rs6000/pcrel-opt.md: Likewise.
* config/rs6000/predicates.md: Likewise.
* ctfc.h: Likewise.
* tree-ssa-uninit.cc: Likewise.
* value-relation.h: Likewise.
* gimple-range-gori.cc: Likewise.
* ipa-polymorphic-call.cc: Likewise.
* pointer-query.cc: Likewise.
* ipa-sra.cc: Likewise.
* internal-fn.cc: Likewise.
* varasm.cc: Likewise.
* gimple-ssa-warn-access.cc: Likewise.
gcc/analyzer/
* store.cc: Fix up duplicated word issue in a comment.
* analyzer.cc: Likewise.
* engine.cc: Likewise.
* sm-taint.cc: Likewise.
gcc/c-family/
* c-attribs.cc: Fix up duplicated word issue in a comment.
gcc/cp/
* cvt.cc: Fix up duplicated word issue in a comment.
* pt.cc: Likewise.
* module.cc: Likewise.
* coroutines.cc: Likewise.
gcc/fortran/
* trans-expr.cc: Fix up duplicated word issue in a comment.
* gfortran.h: Likewise.
* scanner.cc: Likewise.
gcc/jit/
* libgccjit.h: Fix up duplicated word issue in a comment.
This reverts the reversion of r10-5979 amending the CTOR case
with a comment as to why the conversion is not necessary there.
It also adds a testcase (but not for the CTOR case).
2022-03-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/104782
* tree-vect-slp.cc (vectorize_slp_instance_root_stmt):
Re-instantiate r10-5979 fix, add comment.
* gcc.dg/vect/pr104782.c: New testcase.
PR target/104794
gcc/ChangeLog:
* config/arm/arm-builtins.cc (arm_expand_builtin): Reuse error
message. Fix ARM_BUILTIN_WRORHI and ARM_BUILTIN_WRORH that can
have only range [0,32].
The following testcase fails to assemble due to clgte %r6,0(%r1,%r10)
insn not being accepted by assembler.
My rough understanding is that in the RSY-b insn format the spot
in other formats used for index registers is used instead for M3 what
kind of comparison it is, so this patch follows what other similar
instructions use for constraint (i.e. one without index register).
2022-03-07 Jakub Jelinek <jakub@redhat.com>
PR target/104775
* config/s390/s390.md (*cmp_and_trap_unsigned_int<mode>): Use
S constraint instead of T in the last alternative.
* gcc.target/s390/pr104775.c: New test.
PR translation/90148
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_linux64_override_options): Put
quote to a proper place.
* plugin.cc (default_plugin_dir_name): Likewise.
gcc/fortran/ChangeLog:
* intrinsic.cc (gfc_is_intrinsic): Put
quote to a proper place.
The following testcase ICEs, because the cond_andv* expander
has vector_operand predicates in both of the commutative inputs
and calls gen_andv*_mask which calls ix86_binary_operator_ok
in its condition, but nothing calls ix86_fixup_binary_operands_no_copy
during the expansion, which means cond_* accepts even operands
like 2 MEMs which then can't be matched.
The following patch handles it like most other insns that the other
cond_* patterns use - by having a separate define_expand that calls
ix86_fixup_binary_operands_no_copy and define_ins with
ix86_binary_operator_ok.
2022-03-07 Jakub Jelinek <jakub@redhat.com>
PR target/104779
* config/i386/sse.md (avx512dq_mul<mode>3<mask_name>): New
define_expand pattern. Rename define_insn to ...
(*avx512dq_mul<mode>3<mask_name>): ... this.
(<code><mode>3_mask): New any_logic define_expand pattern.
(<mask_codefor><code><mode>3<mask_name>): Rename to ...
(*<code><mode>3<mask_name>): ... this.
* gcc.target/i386/pr104779.c: New test.
There doesn't seem to be any reason for this TU to include
<iostream>, and it causes errors when the resulting libstdc++ is used
on our VxWorks 5.5 target - presumably because now libstdc++ itself
contains an instance of std::ios_base::Init. Which should be mostly
harmless, but apparently isn't, and from a QoI viewpoint should
probably be avoided anyway.
libstdc++-v3/ChangeLog:
* config/locale/vxworks/ctype_members.cc: Remove <iostream>
include.
This updates gcc.dg/lower-subreg-1.c to reflect that the i386 backend now
lowers iordi3 itself, rather than relying on the middle-end's subreg1 pass.
Committed as obvious.
2022-03-06 Roger Sayle <roger@nextmovesoftware.com>
gcc/testsuite/ChangeLog
* gcc.dg/lower-subreg-1.c: Update test case. iordi3 is no longer
lowered by the RTL subreg1 pass on ia32 [even with -mno-stv].
This ensures there's no linker error if libstdc++ headers are included
following a pragma that sets hidden visibility.
Similarly for std::__terminate, which is always-inline so shouldn't
matter, but it's not wrong to do this anyway.
libstdc++-v3/ChangeLog:
* include/bits/c++config (__glibcxx_assert_fail): Add visibility
attribute.
(__terminate): Likewise.
On Fri, Mar 04, 2022 at 02:58:37PM +0100, Jakub Jelinek via Gcc-patches wrote:
> On Thu, Mar 03, 2022 at 05:08:30PM -0700, Martin Sebor wrote:
> > > 1) shouldn't it give up for EDGE_ABNORMAL too? I mean, e.g.
> > > following a non-local goto forced edge from a noreturn call
> > > to a non-local label (if there is just one) doesn't seem
> > > right to me
> >
> > Possibly yes. I can add it but I don't have a lot of experience with
> > these bits so if you can suggest a test case to exercise this that
> > would be helpful.
>
> Something like:
> void
> foo (void)
> {
> __label__ l;
> __attribute__((noreturn)) void bar (int x) { if (x) goto l; __builtin_trap (); }
> bar (0);
> l:;
> }
> shows a single EDGE_ABNORMAL from the bar call.
> But it would need tweaking for the ptr use and clobber.
>
> > > 2) if EDGE_DFS_BACK is computed and 1) is done, is there any
> > > reason why you need 2 levels of protection, i.e. the EDGE_DFS_BACK
> > > check as well as the visited bitmap (and having them use
> > > very different answers, if EDGE_DFS_BACK is seen, the function
> > > will return false, if visited bitmap has a bb, it will return true)?
> > > Can't the visited bitmap go away?
> >
> > Possibly. As I said above, I don't have enough experience with these
> > bits to make (and test) the changes quickly, or enough bandwidth to
> > come up to speed on them. Please feel free to make these improvements.
>
> I'll change that if it passes testing.
Here is a patch to do both. I don't think we really need to have a testcase
for the EDGE_ABNORMAL case (Martin, feel free to add it later), abnormal
edges simply aren't normal control flow and what exactly it means varies.
2022-03-05 Jakub Jelinek <jakub@redhat.com>
* gimple-ssa-warn-access.cc (pass_waccess::use_after_inval_p): Remove
visited bitmap and its use. Also punt on EDGE_ABNORMAL edges.
This clean-up patch resolves PR testsuite/104732, the failure of the recent
test gcc.target/i386/pr100711-1.c on 32-bit Solaris/x86. Rather than just
tweak the testcase, the proposed approach is to fix the underlying problem
by removing the "TARGET_STV && TARGET_SSE2" conditionals from the DI mode
logical operation expanders and pre-reload splitters in i386.md, which as
I'll show generate inferior code (even a GCC 12 regression) on !TARGET_64BIT
whenever -mno-stv (such as Solaris) or -msse (but not -msse2).
First a little bit of history. In the beginning, DImode operations on
i386 weren't defined by the machine description, and lowered during RTL
expansion to SI mode operations. The with PR 65105 in 2015, -mstv was
added, together with a SWIM1248x mode iterator (later renamed to SWIM1248x)
together with several *<code>di3_doubleword post-reload splitters that
made use of register allocation to perform some double word operations
in 64-but XMM registers. A short while later in 2016, PR 70322 added
similar support for one_cmpldi2. All of this logic was dependent upon
"!TARGET_64BIT && TARGET_STV && TARGET_SSE2". With the passing of time,
these conditions became irrelevant when in 2019, it was decided to split
these double-word patterns before reload.
https://gcc.gnu.org/pipermail/gcc-patches/2019-June/523877.htmlhttps://gcc.gnu.org/pipermail/gcc-patches/2019-October/532236.html
Hence the current situation, where on most modern CPU architectures
(where "TARGET_STV && TARGET_SSE2" is true), RTL is expanded with DI
mode operations, that are then split into two SI mode instructions
before reload, except on Solaris and other odd cases, where the splitting
is to two SI mode instructions is done during RTL expansion. By the
time compilation reaches register allocation both paths in theory
produce identical or similar code, so the vestigial legacy/logic would
appear to be harmless.
Unfortunately, there is one place where this arbitrary choice of how
to lower DI mode doubleword operations is visible to the middle-end,
it controls whether the backend appears to have a suitable optab, and
the presence (or not) of DImode optabs can influence vectorization
cost models and veclower decisions.
The issue (and code quality regression) can be seen in this test case:
typedef long long v2di __attribute__((vector_size (16)));
v2di x;
void foo (long long a)
{
v2di t = {a, a};
x = ~t;
}
which when compiled with "-O2 -m32 -msse -march=pentiumpro" produces:
foo: subl $28, %esp
movl %ebx, 16(%esp)
movl 32(%esp), %eax
movl %esi, 20(%esp)
movl 36(%esp), %edx
movl %edi, 24(%esp)
movl %eax, %esi
movl %eax, %edi
movl %edx, %ebx
movl %edx, %ecx
notl %esi
notl %ebx
movl %esi, (%esp)
notl %edi
notl %ecx
movl %ebx, 4(%esp)
movl 20(%esp), %esi
movl %edi, 8(%esp)
movl 16(%esp), %ebx
movl %ecx, 12(%esp)
movl 24(%esp), %edi
movss 8(%esp), %xmm1
movss 12(%esp), %xmm2
movss (%esp), %xmm0
movss 4(%esp), %xmm3
unpcklps %xmm2, %xmm1
unpcklps %xmm3, %xmm0
movlhps %xmm1, %xmm0
movaps %xmm0, x
addl $28, %esp
ret
Importantly notice the four "notl" instructions. With this patch:
foo: subl $28, %esp
movl 32(%esp), %edx
movl 36(%esp), %eax
notl %edx
movl %edx, (%esp)
notl %eax
movl %eax, 4(%esp)
movl %edx, 8(%esp)
movl %eax, 12(%esp)
movaps (%esp), %xmm1
movaps %xmm1, x
addl $28, %esp
ret
Notice only two "notl" instructions. Checking with godbolt.org, GCC
generated 4 NOTs in GCC 4.x and 5.x, 2 NOTs between GCC 6.x and 9.x,
and regressed to 4 NOTs since GCC 10.x [which hopefully qualifies
this clean-up as suitable for stage 4].
Most significantly, this patch allows pr100711-1.c to pass with
-mno-stv, allowing pandn to be used with V2DImode on Solaris/x86.
Fingers-crossed this should reduce the number of discrepancies
encountered supporting Solaris/x86.
2022-03-05 Roger Sayle <roger@nextmovesoftware.com>
Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog
PR testsuite/104732
* config/i386/i386.md (SWIM1248x): Renamed from SWIM1248s.
Include DI mode unconditionally.
(*anddi3_doubleword): Remove && TARGET_STV && TARGET_SSE2 condition,
i.e. always split on !TARGET_64BIT.
(*<any_or>di3_doubleword): Likewise.
(*one_cmpldi2_doubleword): Likewise.
(and<mode>3 expander): Update to use SWIM1248x from SWIM1248s.
(<any_or><mode>3 expander): Likewise.
(one_cmpl<mode>2 expander): Likewise.
gcc/testsuite/ChangeLog
PR testsuite/104732
* gcc.target/i386/pr104732.c: New test case.
On power10, GCC tries to optimize the signed conversion from DImode to
TImode by using the vextsd2q instruction. However to generate this
instruction, it would have to generate 3 direct moves (1 from the GPR
registers to the altivec registers, and 2 from the altivec registers to
the GPR register).
This patch generates the shift right immediate instruction to do the
conversion if the target/source registers ares GPR registers like it does
on earlier systems. If the target/source registers are Altivec registers,
it will generate the vextsd2q instruction.
2022-03-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/104698
* config/rs6000/vsx.md (UNSPEC_MTVSRD_DITI_W1): Delete.
(mtvsrdd_diti_w1): Delete.
(extendditi2): Convert from define_expand to
define_insn_and_split. Replace with code to deal with both GPR
registers and with altivec registers.
gcc/testsuite/
PR target/104698
* gcc.target/powerpc/pr104698-1.c: New test.
* gcc.target/powerpc/pr104698-2.c: New test.
