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Author	SHA1	Message	Date
Mikael Morin	237380cdec	fortran: Evaluate once BACK argument of MINLOC/MAXLOC with DIM [PR90608] Evaluate the BACK argument of MINLOC/MAXLOC once before the scalarization loops in the case where the DIM argument is present. This is a follow-up to r15-1994-ga55d24b3cf7f4d07492bb8e6fcee557175b47ea3 which added knowledge of BACK to the scalarizer, to r15-2701-ga10436a8404ad2f0cc5aa4d6a0cc850abe5ef49e which removed it to handle it out of scalarization instead, and to more immediate previous patches that added inlining support for MINLOC/MAXLOC with DIM. The inlining support for MINLOC/MAXLOC with DIM introduced nested loops, which made the evaluation of BACK (removed from the scalarizer knowledge by the forementionned commit) wrapped in a loop, so possibly executed more than once. This change adds BACK to the scalarization chain if MINLOC/MAXLOC will use nested loops, so that it is evaluated by the scalarizer only once before the outermost loop in that case. PR fortran/90608 gcc/fortran/ChangeLog: * trans-intrinsic.cc (walk_inline_intrinsic_minmaxloc): Add a scalar element for BACK as first item of the chain if BACK is present and there will be nested loops. (gfc_conv_intrinsic_minmaxloc): Evaluate BACK using an inherited scalarization chain if there is a nested loop. gcc/testsuite/ChangeLog: * gfortran.dg/maxloc_8.f90: New test. * gfortran.dg/minloc_9.f90: New test.	2024-11-20 13:59:51 +01:00
Uros Bizjak	086ee8d086	i386: Remove workaround for Solaris ld 64-bit TLS IE limitation As detailed in PR target/43309, the Solaris linker initially took the 64-bit x86 TLS IE code sequence literally, assuming that the spec only allowed %rax as target register. A workaround has been in place for more than a decade, but is no longer necessary. The bug had already been fixed for Solaris 11.1, while trunk requires Solaris 11.4. Uros pointed this out and suggested the attached patch. Bootstrapped without regressions on i386-pc-solaris2.11. 2024-10-15 Uros Bizjak <ubizjak@gmail.com> gcc: * config/i386/i386.cc (legitimize_tls_address) <TLS_MODEL_INITIAL_EXEC>: Remove 64-bit Solaris ld workaround. * config/i386/i386.md (UNSPEC_TLS_IE_SUN): Remove. (tls_initial_exec_64_sun): Remove.	2024-11-20 12:57:25 +01:00
Rainer Orth	bf57f9b599	testsuite: i386: Fix gcc.target/i386/pr117232-1.c etc. with Solaris as Two tests FAIL on Solaris/x86 with the native assembler: FAIL: gcc.target/i386/pr117232-1.c scan-assembler-times (?n)cmovn?c 7 FAIL: gcc.target/i386/pr117232-apx-1.c scan-assembler-times (?n)cmovn?c 7 The problem is that as expects a slightly different insn syntax, e.g. cmovl.nc %esi, %eax instead of cmovnc %esi, %eax This patch allows for both forms. Tested on i386-pc-solaris2.11 (as and gas) and x86_64-pc-linux-gnu. 2024-11-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> gcc/testsuite: * gcc.target/i386/pr117232-1.c (scan-assembler-times): Allow for cmovl.nc etc. * gcc.target/i386/pr117232-apx-1.c: Likewise.	2024-11-20 12:54:22 +01:00
Pan Li	fa18217f60	RISC-V: Refine the rtl dump expand check for vector SAT_ADD This patch would like to remove the unnecessary option for the vector SAT_ADD testcases at first. And the different optimization option like O2 and O3 will be passed to the test files for rtl expand dump check. If there are different dump check times for different optimization options, the target no-opts and/or any-opts will be leveraged for the dg-final check. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Remove the unnecessary option and refine the rtl IFN dump check. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>	2024-11-20 19:27:16 +08:00
Pan Li	b95d585fd4	RISC-V: Introduce riscv/rvv/autovec/sat folder to rvv.exp testsuite After we move vector SAT_ADD testcases into a isolated folder, aka riscv/rvv/autovec/sat. We would like to add the folder as one of the test items of the rvv.exp testsuite. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add the vector sat folder to the rvv.exp testsuite. Signed-off-by: Pan Li <pan2.li@intel.com>	2024-11-20 19:27:09 +08:00
Pan Li	42f1a08e41	RISC-V: Rearrange the test files for vector SAT_ADD [NFC] The test files of scalar SAT_TRUNC only has numbers as the suffix. Rearrange the file name to -{form number}-{target-type}. For example, test form 3 for uint32_t SAT_TRUNC will have -3-u32.c for asm check and -run-3-u32.c for the run test. Meanwhile, all related test files moved to riscv/rvv/autovec/sat/. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-16.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-2.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-3.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-4.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-1.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-6.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-7.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-8.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-5.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-10.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-11.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-12.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-9.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-14.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-15.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-13.c: Move to... * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: ...here. * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: New test. * gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vvv_run.h: New test. * gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vvx_run.h: New test. * gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vx_run.h: New test. * gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: New test. Signed-off-by: Pan Li <pan2.li@intel.com>	2024-11-20 19:27:02 +08:00
Richard Biener	ff5a14abeb	tree-optimization/117574 - bougs niter lt-to-ne When trying to change a IV from IV0 < IV1 to IV0' != IV1' we apply fancy adjustments to the may_be_zero condition we compute rather than using the obvious IV0->base >= IV1->base expression (to be able to use > instead of >=?). This doesn't seem to go well. PR tree-optimization/117574 * tree-ssa-loop-niter.cc (number_of_iterations_lt_to_ne): Use the obvious may_be_zero condition. * gcc.dg/torture/pr117574-1.c: New testcase.	2024-11-20 11:24:26 +01:00
Richard Sandiford	ed6d0867fd	Extend expand_absneg_bit to vector modes Expand can implement NEG and ABS of scalar floating-point modes by using logic ops to manipulate the sign bit. This patch extends that approach to vectors, since it fits relatively easily into the same structure. The motivating use case was to inline bf16 NEG and ABS operations for AArch64. The patch includes tests for that. get_absneg_bit_mode required a new opt_mode constructor, so that opt_mode<T> can be constructed from opt_mode<U> if T is no less general than U. gcc/ * machmode.h (opt_mode::opt_mode): New overload. * optabs-query.h (get_absneg_bit_mode): Declare. * optabs-query.cc (get_absneg_bit_mode): New function, split out from expand_absneg_bit. (can_open_code_p): Use get_absneg_bit_mode. * optabs.cc (expand_absneg_bit): Likewise. Take an outer and inner mode, rather than just one. Handle vector modes. (expand_unop, expand_abs_nojump): Update calls accordingly. Handle vector modes. gcc/testsuite/ * gcc.target/aarch64/abs_bf_1.c: New test. * gcc.target/aarch64/neg_bf_1.c: Likewise. * gcc.target/aarch64/neg_bf_2.c: Likewise.	2024-11-20 10:04:46 +00:00
Richard Sandiford	0abb5fa523	Use can_implement_p in the vectoriser This patch goes through the tree-vect-* code and mechanically replaces all tests of optab_handler against CODE_FOR_nothing with calls to the new helper functions. gcc/ * tree-vect-data-refs.cc (vect_supportable_dr_alignment): Use can_implement_p instead of optab_handler. * tree-vect-generic.cc (add_rshift, expand_vector_divmod): Likewise. (optimize_vector_constructor, type_for_widest_vector_mode): Likewise. (lower_vec_perm, expand_vector_operations_1): Likewise. * tree-vect-loop.cc (have_whole_vector_shift): Likewise. * tree-vect-patterns.cc (vect_recog_rotate_pattern): Likewise. (target_has_vecop_for_code, vect_recog_mult_pattern): Likewise. (vect_recog_divmod_pattern): Likewise. * tree-vect-stmts.cc (vect_supportable_shift, vectorizable_shift) (scan_store_can_perm_p, check_scan_store, vectorizable_store) (vectorizable_load, vectorizable_condition): Likewise. (vectorizable_comparison_1): Likewise.	2024-11-20 10:04:45 +00:00
Richard Sandiford	485ab50c20	Add helpers to test whether an optab can be implemented The vectoriser and vector lowering passes both had tests of the form: if (op && (optab_handler (op, compute_mode) != CODE_FOR_nothing \|\| optab_libfunc (op, compute_mode))) ...success... if (code == MULT_HIGHPART_EXPR && can_mult_highpart_p (compute_mode, TYPE_UNSIGNED (compute_type))) ...success... This patch adds helper routines for this kind of test, so that it's easier to handle other optab alternatives in a similar way. gcc/ * optabs-query.cc (can_open_code_p, can_implement_p): Declare. * optabs-query.h (can_open_code_p, can_implement_p): New functions. * optabs-tree.cc (target_supports_op_p): Use can_implement_p. * tree-vect-stmts.cc (vectorizable_operation): Likewise. * tree-vect-generic.cc (get_compute_type): Likewise. Remove code parameter. (expand_vector_scalar_condition, expand_vector_conversion) (expand_vector_operations_1): Update calls accordingly.	2024-11-20 10:04:45 +00:00
Andre Vieira	3ec0b7cd7c	arm, mve: Fix arm_mve_dlstp_check_dec_counter's use of single_pred Call 'single_pred_p' before 'single_pred' to verify it is safe to do so. gcc/ChangeLog: * config/arm/arm.cc (arm_mve_dlstp_check_dec_counter): Call single_pred_p to verify it's safe to call single_pred. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/dlstp-loop-form.c: Add loop that triggered ICE.	2024-11-20 09:23:50 +00:00
Mikael Morin	95b5fd7316	fortran: Check for empty MINLOC/MAXLOC ARRAY along DIM only In the function generating inline code to implement MINLOC and MAXLOC, only check for ARRAY size along DIM if DIM is present. The check for ARRAY emptyness had been checking the size of the full array, which is correct for MINLOC and MAXLOC without DIM. But if DIM is present, the reduction is along DIM only so the check for emptyness should consider that dimension only as well. This sounds like a correctness issue, but fortunately the cases where it makes a difference are cases where ARRAY is empty, so even if the value calculated for MINLOC or MAXLOC is wrong, it's wrapped in a zero iteration loop, and the wrong values are not actually used. In the end this just avoids unnecessary calculations. A previous version of this patch regressed on non-constant DIM with rank 1 ARRAY. The new testcase checks that that case is supported. gcc/fortran/ChangeLog: * trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Only get the size along DIM instead of the full size if DIM is present. gcc/testsuite/ChangeLog: * gfortran.dg/minmaxloc_22.f90: New test.	2024-11-20 10:12:21 +01:00
Feng Wang	323adc0fc4	PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error This patch fix the wrong condition for RVVMF2BF. It should be TARGET_VECTOR_ELEN_BF_16. gcc/ChangeLog: PR target/117669 * config/riscv/vector-iterators.md: Signed-off-by: Feng Wang <wangfeng@eswincomputing.com>	2024-11-20 08:01:03 +00:00
MayShao-oc	6350e956d1	Add microarchtecture tunable for pass_align_tight_loops [PR117438] Hi Hongtao: Add m_CASCADELAK, and m_SKYLAKE_AVX512. Place X86_TUNE_ALIGN_TIGHT_LOOPS in the appropriate section. Bootstrapped X86_64. Ok for trunk? BR Mayshao gcc/ChangeLog: PR target/117438 * config/i386/i386-features.cc (TARGET_ALIGN_TIGHT_LOOPS): default true in all processors except for m_ZHAOXIN, m_CASCADELAKE, and m_SKYLAKE_AVX512. * config/i386/i386.h (TARGET_ALIGN_TIGHT_LOOPS): New Macro. * config/i386/x86-tune.def (X86_TUNE_ALIGN_TIGHT_LOOPS): New tune	2024-11-20 14:52:11 +08:00
Torbjörn SVENSSON	03438f621e	testsuite: arm: Only check for absence of literal pools in no-literal-pool-m0.c With the changes in r15-1579-g792f97b44ff, the constants have been updated. This patch drops the fragile check on the constants and instead only checks that there is no literal pool generated. gcc/testsuite/ChangeLog: * gcc.target/arm/pure-code/no-literal-pool-m0.c: Only check for absence of literal pools. Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>	2024-11-20 07:49:27 +01:00
Jonathan Wakely	f6f28dc41d	libstdc++: Use const_iterator in std::set::find<K> return type François noticed that the "wrong" type is used in the return type for a std::set member function template. The iterator for our std::set is the same type as const_iterator, so this doesn't actually matter. But it's clearer if the return type matches the type used in the function body. libstdc++-v3/ChangeLog: * include/bits/stl_set.h (set::find): Use const_iterator in return type, not iterator.	2024-11-20 06:44:50 +00:00
Jonathan Wakely	4484945c53	libstdc++: Fix std::unordered_set::emplace optimization [PR117686] The __is_key_type specialization that matches a pair<key_type, T> argument is intended for std::unordered_map, not for std::unordered_set<std::pair<K,T>>. This uses a pair<const Args&...> as the template argument for __is_key_type, so that it won't match a set's key_type. libstdc++-v3/ChangeLog: PR libstdc++/117686 * include/bits/hashtable.h (_Hashtable::_M_emplace_uniq): Adjust usage of __is_key_type to avoid false positive. * testsuite/23_containers/unordered_set/insert/117686.cc: New test.	2024-11-20 06:44:43 +00:00
Pan Li	7c7da10365	RISC-V: Refine the rtl expand check for strided ld/st This patch would like to remove the unnecessary option for the strided load/store testcases. After fix the option from the rvv.exp, both the O2 and O3 will be passed to the test files for rtl expand dump check but the O2 has 2 time for IFN while the O3 has 4 times with -fvectorize specificed. Thus, add xfail O2 for IFN 4 times check, as well as xfail O3 for 2 times check. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Remove unnecessary optimization option and xfail O2/O3 diff IFN times from the rtl expand dump. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>	2024-11-20 12:20:00 +08:00
Pan Li	c10767d0e4	RISC-V: Fix incorrect optimization options passing to strided ld/st test The testcases of vector strided load/store are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of gcc.log. This patch would like to make it correct, and then you will see the build option similar as below from the gcc.log. Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic ... Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 ... The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options. Signed-off-by: Pan Li <pan2.li@intel.com>	2024-11-20 12:19:48 +08:00
yulong	139bd3198a	RISC-V: Add the mini support for SiFive extensions. This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and xsfvfnrclipxfqf extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New. * config/riscv/riscv.opt: New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-sf-3.c: New test. * gcc.target/riscv/predef-sf-4.c: New test. * gcc.target/riscv/predef-sf-5.c: New test.	2024-11-20 12:02:25 +08:00
Jeff Law	065433b4ce	[RISC-V][PR target/117649] Fix branch on masked values splitter Andreas reported GCC mis-compiled GAS for risc-v Thankfully he also reduced it to a nice little testcase. So the whole point of the pattern in question is to "reduce" the constants by right shifting away common unnecessary bits in RTL expressions like this: > [(set (pc) > (if_then_else (any_eq > (and:ANYI (match_operand:ANYI 1 "register_operand" "r") > (match_operand 2 "shifted_const_arith_operand" "i")) > (match_operand 3 "shifted_const_arith_operand" "i")) > (label_ref (match_operand 0 "" "")) > (pc))) When applicable, the reduced constants in operands 2/3 fit into a simm12 and thus do not need multi-instruction synthesis. Note that we have to also shift operand 1. That shift should have been an arithmetic shift, but was incorrectly coded as a logical shift. Fixed with the obvious change on the right shift opcode. Expecting to push to the trunk once the pre-commit tester renders its verdict. I've already tested in this my tester for rv32 and rv64. PR target/117649 gcc/ * config/riscv/riscv.md (branch on masked/shifted operands): Use arithmetic rather than logical shift for operand 1. gcc/testsuite * gcc.target/riscv/branch-1.c: Update expected output. * gcc.target/riscv/pr117649.c: New test.	2024-11-19 19:26:08 -07:00
Joseph Myers	5afc98fec9	c: Fix ICE for integer constexpr initializers of wrong type [PR115515] Bug 115515 (plus its duplicate 117139) reports an ICE with constexpr initializer for an integer type variable that is not of integer type. Fix this by not calling int_fits_type_p unless the previous check for an integer constant expression passes. Bootstrapped with no regressions for x86_64-pc-linux-gnu. PR c/115515 gcc/c/ * c-typeck.cc (check_constexpr_init): Do not call int_fits_type_p for arguments that are not integer constant expressions. gcc/testsuite/ * gcc.dg/c23-constexpr-10.c, gcc.dg/gnu23-constexpr-2.c: New tests.	2024-11-20 01:39:06 +00:00
Pan Li	357708c653	RISC-V: Remove unnecessary option for all other scalar SAT_* testcase After we create a isolated folder to hold all SAT scalar test, we have fully control of what optimization options passing to the testcase. Thus, it is better to remove the unnecessary work around for flto option, as well as the -O3 option for each cases. The riscv.exp will pass sorts of different optimization options for each case. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_s_sub-1-i16.c: Remove flto dg-skip workaround and -O3 option. * gcc.target/riscv/sat/sat_s_sub-1-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-1-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-1-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-2-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-2-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-2-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-2-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-3-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-3-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-3-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-3-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-4-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-4-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-4-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-4-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>	2024-11-20 09:35:41 +08:00
Pan Li	b4462fd8eb	RISC-V: Rearrange the rest of test files for scalar SAT_* [NFC] Move all the other files of scalar SAT to dir riscv/sat/. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_s_sub-1-i16.c: Move to... * gcc.target/riscv/sat/sat_s_sub-1-i16.c: ...here. * gcc.target/riscv/sat_s_sub-1-i32.c: Move to... * gcc.target/riscv/sat/sat_s_sub-1-i32.c: ...here. * gcc.target/riscv/sat_s_sub-1-i64.c: Move to... * gcc.target/riscv/sat/sat_s_sub-1-i64.c: ...here. * gcc.target/riscv/sat_s_sub-1-i8.c: Move to... * gcc.target/riscv/sat/sat_s_sub-1-i8.c: ...here. * gcc.target/riscv/sat_s_sub-2-i16.c: Move to... * gcc.target/riscv/sat/sat_s_sub-2-i16.c: ...here. * gcc.target/riscv/sat_s_sub-2-i32.c: Move to... * gcc.target/riscv/sat/sat_s_sub-2-i32.c: ...here. * gcc.target/riscv/sat_s_sub-2-i64.c: Move to... * gcc.target/riscv/sat/sat_s_sub-2-i64.c: ...here. * gcc.target/riscv/sat_s_sub-2-i8.c: Move to... * gcc.target/riscv/sat/sat_s_sub-2-i8.c: ...here. * gcc.target/riscv/sat_s_sub-3-i16.c: Move to... * gcc.target/riscv/sat/sat_s_sub-3-i16.c: ...here. * gcc.target/riscv/sat_s_sub-3-i32.c: Move to... * gcc.target/riscv/sat/sat_s_sub-3-i32.c: ...here. * gcc.target/riscv/sat_s_sub-3-i64.c: Move to... * gcc.target/riscv/sat/sat_s_sub-3-i64.c: ...here. * gcc.target/riscv/sat_s_sub-3-i8.c: Move to... * gcc.target/riscv/sat/sat_s_sub-3-i8.c: ...here. * gcc.target/riscv/sat_s_sub-4-i16.c: Move to... * gcc.target/riscv/sat/sat_s_sub-4-i16.c: ...here. * gcc.target/riscv/sat_s_sub-4-i32.c: Move to... * gcc.target/riscv/sat/sat_s_sub-4-i32.c: ...here. * gcc.target/riscv/sat_s_sub-4-i64.c: Move to... * gcc.target/riscv/sat/sat_s_sub-4-i64.c: ...here. * gcc.target/riscv/sat_s_sub-4-i8.c: Move to... * gcc.target/riscv/sat/sat_s_sub-4-i8.c: ...here. * gcc.target/riscv/sat_s_sub-run-1-i16.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-1-i16.c: ...here. * gcc.target/riscv/sat_s_sub-run-1-i32.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-1-i32.c: ...here. * gcc.target/riscv/sat_s_sub-run-1-i64.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-1-i64.c: ...here. * gcc.target/riscv/sat_s_sub-run-1-i8.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-1-i8.c: ...here. * gcc.target/riscv/sat_s_sub-run-2-i16.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-2-i16.c: ...here. * gcc.target/riscv/sat_s_sub-run-2-i32.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-2-i32.c: ...here. * gcc.target/riscv/sat_s_sub-run-2-i64.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-2-i64.c: ...here. * gcc.target/riscv/sat_s_sub-run-2-i8.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-2-i8.c: ...here. * gcc.target/riscv/sat_s_sub-run-3-i16.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-3-i16.c: ...here. * gcc.target/riscv/sat_s_sub-run-3-i32.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-3-i32.c: ...here. * gcc.target/riscv/sat_s_sub-run-3-i64.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-3-i64.c: ...here. * gcc.target/riscv/sat_s_sub-run-3-i8.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-3-i8.c: ...here. * gcc.target/riscv/sat_s_sub-run-4-i16.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-4-i16.c: ...here. * gcc.target/riscv/sat_s_sub-run-4-i32.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-4-i32.c: ...here. * gcc.target/riscv/sat_s_sub-run-4-i64.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-4-i64.c: ...here. * gcc.target/riscv/sat_s_sub-run-4-i8.c: Move to... * gcc.target/riscv/sat/sat_s_sub-run-4-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-1-i16-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-1-i32-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-1-i32-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-1-i64-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-1-i64-to-i32.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c: ...here. * gcc.target/riscv/sat_s_trunc-1-i64-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-2-i16-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-2-i32-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-2-i32-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-2-i64-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-2-i64-to-i32.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c: ...here. * gcc.target/riscv/sat_s_trunc-2-i64-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-3-i16-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-3-i32-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-3-i32-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-3-i64-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-3-i64-to-i32.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c: ...here. * gcc.target/riscv/sat_s_trunc-3-i64-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-4-i16-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-4-i32-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-4-i32-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-4-i64-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-4-i64-to-i32.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c: ...here. * gcc.target/riscv/sat_s_trunc-4-i64-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-5-i16-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-5-i32-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-5-i32-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-5-i64-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-5-i64-to-i32.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c: ...here. * gcc.target/riscv/sat_s_trunc-5-i64-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-6-i16-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-6-i32-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-6-i32-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-6-i64-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c: ...here. * gcc.target/riscv/sat_s_trunc-6-i64-to-i32.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c: ...here. * gcc.target/riscv/sat_s_trunc-6-i64-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-7-i16-to-i8.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c: ...here. * gcc.target/riscv/sat_s_trunc-7-i32-to-i16.c: Move to... * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c: ...here. * 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Signed-off-by: Pan Li <pan2.li@intel.com>	2024-11-20 09:35:41 +08:00
GCC Administrator	b597edbdfb	Daily bump.	2024-11-20 00:19:59 +00:00
Mikael Morin	f5a87c8d8c	fortran: Inline non-character MINLOC/MAXLOC with DIM [PR90608] Enable generation of inline MINLOC/MAXLOC code in the cases where DIM is a constant, and either ARRAY is of REAL type or MASK is an array. Those cases are the remaining bits to fully support inlining of non-CHARACTER MINLOC/MAXLOC with constant DIM. They are treated together because they generate similar code, the NANs for REAL types being handled a bit like a second level of masking. These are the cases for which we generate two loops. This change affects the code generating the second loop, that was previously accessible only in cases ARRAY had rank 1. The main changes are in gfc_conv_intrinsic_minmaxloc the replacement of the locally initialized scalarization loop with the one provided and previously initialized by the scalarizer. Same goes for the locally initialized MASK scalarizer chain. As this is enabling the code generating a second loop in a context of reduction and nested loops, care is taken not to advance the parent scalarization chain twice. The scalarization chain element(s) for an array MASK are inserted in the chain at a different place from that of a scalar MASK. This is done on purpose to match the code consuming the chains which are in different places for scalar and array MASK. PR fortran/90608 gcc/fortran/ChangeLog: * trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Return TRUE for MINLOC/MAXLOC with constant DIM and either REAL ARRAY or non-scalar MASK. (walk_inline_intrinsic_minmaxloc): Walk MASK and if it's an array add the chain obtained before that of ARRAY. (gfc_conv_intrinsic_minmaxloc): Use the nested loop if there is one. To evaluate MASK (respectively ARRAY in the second loop), inherit the scalarizer chain if in a nested loop, otherwise keep using the chain obtained by walking MASK (respectively ARRAY). If there is a nested loop, avoid advancing the parent scalarization chain a second time in the second loop. gcc/testsuite/ChangeLog: * gfortran.dg/minmaxloc_21.f90: New test.	2024-11-19 22:39:11 +01:00
Joseph Myers	933b146f0a	c: Do not register nullptr_t built-in type [PR114869] As reported in bug 114869, the C front end wrongly creates nullptr_t as a built-in typedef; it should only be defined in <stddef.h>. While the type node needs a name for debug info generation, it doesn't need to be a valid identifier; use typeof (nullptr) instead, similar to how the C++ front end uses decltype(nullptr) for this purpose. Bootstrapped with no regressions for x86_64-pc-linux-gnu. PR c/114869 gcc/c/ * c-decl.cc (c_init_decl_processing): Register nullptr_type_node as typeof (nullptr) not nullptr_t. gcc/testsuite/ * gcc.dg/c23-nullptr-5.c: Use typeof (nullptr) not nullptr_t. * gcc.dg/c11-nullptr-2.c, gcc.dg/c11-nullptr-3.c, gcc.dg/c23-nullptr-7.c: New tests	2024-11-19 21:31:24 +00:00
Georg-Johann Lay	b222ee1004	AVR: target/54378 - Reconsider the default shift costs. This patch calculates more accurate shift costs, but makes the costs for larger offsets no more expensive than the costs for an unrolled shift. gcc/ PR target/54378 * config/avr/avr.cc (avr_default_shift_costs): New static function. (avr_rtx_costs_1) [ASHIFT, LSHIFTRT, ASHIFTRT]: Use it to determine the default shift costs for shifts with a constant shift offset.	2024-11-19 21:34:06 +01:00
Mikael Morin	83da0a00d1	fortran: Check MASK directly instead of its scalarization chain Update the conditions used by the inline MINLOC/MAXLOC code generation function to check directly the properties of MASK instead of the variable holding its scalarization chain. The inline implementation of MINLOC/MAXLOC in gfc_conv_intrinsic_minmaxloc uses several conditions checking the presence of a scalarization chain for MASK, which means that the argument is present and non-scalar. The next patch will allow inlining MINLOC/MAXLOC with DIM and MASK, and in that case the scalarization chain for MASK is initialized elsewhere, so the variable usually holding it in the function is not used, and the conditions won't work in that case. This change updates the conditions to check directly the properties of MASK so that they work even if the scalarization chain variable is not used. gcc/fortran/ChangeLog: * trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Use conditionals based on the MASK expression rather than on its scalarization chains.	2024-11-19 21:17:37 +01:00
Jakub Jelinek	8663fc1c28	c-family: Fix ICE with __sync__and_ on _BitInt [PR117641] Only __atomic_* builtins are meant to work on arbitrary _BitInt types (if not supported in hw we emit a CAS loop which uses __atomic_load_* in that case), the compatibility __sync_* builtins work only if there is a corresponding normal integral type (for _BitInt on 32-bit ARM we'll need to limit even that to no padding, because the padding bits are well defined there and the hw or libatomic __sync_* APIs don't guarantee that), IMHO people shouldn't mix very old APIs with very new ones and I don't see a replacement for the __atomic_load_. For size > 16 that is how it already correctly behaves, in the hunk shown in the patch it is immediately followed by if (fetch && !orig_format && TREE_CODE (type) == BITINT_TYPE) return -1; which returns -1 for the __atomic_ builtins (i.e. !orig_format), which causes caller to use atomic_bitint_fetch_using_cas_loop, and otherwise does diagnostic and return 0 (which causes caller to punt). But for size == 16 if TImode isn't suipported (i.e. mostly 32-bit arches), we return (correctly) -1 if !orig_format, so again force atomic_bitint_fetch_using_cas_loop on those arches for e.g. _BitInt(115), but for orig_format the function returns 16 as if it could do 16 byte __sync__and_ (which it can't because TImode isn't supported; for 16 byte it can only do (perhaps using libatomic) normal compare and swap). So we need to error and return 0, rather than return 16. The following patch ensures that. 2024-11-19 Jakub Jelinek <jakub@redhat.com> PR c/117641 * c-common.cc (sync_resolve_size): For size == 16 fetch of BITINT_TYPE if TImode isn't supported scalar mode diagnose and return 0 if orig_format instead of returning 16. * gcc.dg/bitint-115.c: New test.	2024-11-19 20:36:00 +01:00
Jakub Jelinek	02fff24e2c	c: Fix up __builtin_stdc_rotate_{left,right} lowering [PR117456] Apparently the middle-end/expansion can only handle {L,R}ROTATE_EXPR on types with mode precision, or large/huge BITINT_TYPE. So, the following patch uses the rotate exprs only in those cases where it can be handled, and emits code with shifts/ior otherwise. As types without mode precision including small/medium BITINT_TYPE have unlikely power of two precision and TRUNC_MOD_EXPR is on many targets quite expensive, I chose to expand e.g. __builtin_stdc_rotate_left (arg1, arg2) as ((tem = arg1, count = arg2 % prec) ? ((tem << count) \| (tem >> (prec - count))) : tem) rather than (((tem = arg1) << (count = arg2 % prec)) \| (tem >> (-count % prec)) (where the assignments are really save_exprs, so no UB), because I think another TRUNC_MOD_EXPR would be more costly in most cases when the shift count is non-constant (and when it is constant, it folds to 2 shifts by constant and ior in either case). 2024-11-19 Jakub Jelinek <jakub@redhat.com> PR c/117456 gcc/c/ * c-parser.cc (c_parser_postfix_expression): Use LROTATE_EXPR or RROTATE_EXPR only if type_has_mode_precision_p or if arg1 has BITINT_TYPE with precision larger than MAX_FIXED_MODE_SIZE. Otherwise build BIT_IOR_EXPR of LSHIFT_EXPR and RSHIFT_EXPR and wrap it into a COND_EXPR depending on if arg2 is 0 or not. * c-fold.cc (c_fully_fold_internal): Check for suppression of -Wshift-count-overflow warning. gcc/testsuite/ * gcc.dg/builtin-stdc-rotate-4.c: New test.	2024-11-19 20:34:36 +01:00
Georg-Johann Lay	780720f04b	testsuite/52641 - Skip test cases that are not 16-bit clean. gcc/testsuite/ PR testsuite/52641 PR testsuite/116488 PR testsuite/116915 * gcc.dg/torture/pr116488.c: Require int32plus. * gcc.dg/torture/pr116915.c: Require int32plus.	2024-11-19 19:40:36 +01:00
Martin Uecker	8b02cc9a4f	c: fix incorrect TBAA for tagged types across translation units [PR117490] Two different declarations of tagged types in the same translation unit are incompatible in C before C23 and without tag also in C23. Still, two such types can be compatible to the same tagged type in a different translation unit, but this means that pointers can alias. typedef struct { int i; } s1; typedef struct { int i; } s2; int f(s1 p1, s2 p2) { p1->i = 2; p2->i = 3; // p2->i can alias p1->i return p1->i; } We need to assign the same TYPE_CANONICAL to both types. This patch fixes this for C23 and types without tag by also forming equivalence classes for such types based on their structure as already done for types with tag. Because this change exposes checking errors related to flexible array members (cf. PR113688), one test is restricted to C17 for now. PR c/117490 gcc/c/ChangeLog: * c-typeck.cc (tagged_types_tu_compatible): Form equivalence classed for tagless types in C23. gcc/testsuite/ChangeLog: * gcc.dg/gnu23-tag-alias-4.c: Adapt test. * gcc.dg/gnu23-tag-alias-7.c: Adapt test. * gcc.dg/guality/zero-length-array.c: Restrict to c17. * gcc.dg/pr117490.c: New test.	2024-11-19 19:34:31 +01:00
Eric Botcazou	51d12cc4b6	Enable symbolic backtraces on more Linux and BSD ports gcc/ada PR ada/117538 * Makefile.rtl (GNU Hurd): Add $(TRASYM_DWARF_UNIX_OBJS). (x86-64 kfreebsd): Likewise. (aarch64 FreeBSD): Likewise. (x86-64 DragonFly): Likewise. (S390 Linux): Likewise. (Mips Linux): Likewise. (SPARC Linux): Likewise. (HP/PA Linux): Linux. (M68K Linux): Likewise. (SH4 Linux): Likewise. (Alpha Linux): Likewise. (RISC-V Linux): Likewise.	2024-11-19 18:48:48 +01:00
Edwin Lu	c415686461	RISC-V: testsuite: fix old-style function definition error [NFC] The following testcase was failing with the warning: old-style function definition ever since the c standard version has been updated. Update the function definition. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c: Update function definition. Signed-off-by: Edwin Lu <ewlu@rivosinc.com>	2024-11-19 09:39:22 -08:00
Georg-Johann Lay	9f7b323caa	AVR: Overhaul shift insns. This patch adds 3-operand alternatives to the shift insns for offsets that are one less than the bit-size of the mode. For example, ashrhi3 can support "r,r,C15" without overhead. Apart from that, the asm out functions for the shifts now use avr_asm_len to print assembly and to track the isnsns' lengths. gcc/ * config/avr/avr.md (ashlhi3, ashlhi3_const_split, ashlhi3_const) (ashlpsi3_split, ashlpsi3) (ashlsi3, ashlsi3_const_split, ashlsi3_const) (ashrhi3, ashrhi3, ashrpsi3, ashrpsi3, ashrsi3, ashrsi3) (ashrhi3_const_split, ashrhi3_const, ashrsi3_const_split, ashrsi3_const): Add constraint alternatives that allow a 3-operand operation when the shift offset is one less than the mode's bitsize. config/avr/avr.cc (ashl<mode>3_out, ashr<mode>3_out) (lshr<mode>3_out): Use avr_asm_len for asm_out and length tracking. (ashrhi3_out, ashlhi3_out): Support the new "r,r,C15" alternatives. (ashrsi3_out, ashlsi3_out): Support the new "r,r,C31" alternatives. (avr_out_ashrpsi3, avr_out_ashlpsi3): Support the new "r,r,C23" alternatives. gcc/testsuite/ * gcc.target/avr/torture/test-shift.h: New file. * gcc.target/avr/torture/shift-l-u32.c: New test. * gcc.target/avr/torture/shift-r-u32.c: New test. * gcc.target/avr/torture/shift-r-i32.c: New test. * gcc.target/avr/torture/shift-l-u24.c: New test. * gcc.target/avr/torture/shift-r-u24.c: New test. * gcc.target/avr/torture/shift-r-i24.c: New test. * gcc.target/avr/torture/shift-l-u16.c: New test. * gcc.target/avr/torture/shift-r-u16.c: New test. * gcc.target/avr/torture/shift-r-i16.c: New test. * gcc.target/avr/torture/shift-l-u8.c: New test. * gcc.target/avr/torture/shift-r-u8.c: New test. * gcc.target/avr/torture/shift-r-i8.c: New test.	2024-11-19 18:30:26 +01:00
Georg-Johann Lay	49f4e96996	AVR: Use more bool. Now that the C default is C23, we can use bool in avr.h (which is still used in libgcc via tm.h). bool is a keyword in C23, so no stdbool.h is required in libgcc. gcc/ * config/avr/avr.h (avr_args.has_stack_args): Be a bool. (struct machine_function) <is_naked, is_noblock, is_OS_task, is_OS_task, sibcall_fails, attributes_checked_p, is_no_gccisr, use_L__stack_usage, gasisr.yes, gasisr.maybe>: Same. * config/avr/avr-protos.h (reg_unused_after) (test_hard_reg_class, jump_over_one_insn_p): Use bool as return type. * config/avr/avr.cc (reg_unused_after) (test_hard_reg_class, jump_over_one_insn_p): Same. (cfun->machine->attributes_checked_p, cum->has_stack_args) (cfun->machine->use_L__stack_usage, cfun->machine->gasisr.yes) (cfun->machine->sibcall_fails): Use like a bool.	2024-11-19 18:26:44 +01:00
Dimitar Dimitrov	c9530a0e24	RISC-V: Tie MUL and DIV masks to the M extension When configuring GCC for RV32EC with: ./configure \ --target=riscv32-none-elf \ --with-multilib-generator="rv32ec-ilp32e--" \ --with-abi=ilp32e \ --with-arch=rv32ec Then the build fails because division is erroneously left enabled: cc1: error: '-mdiv' requires '-march' to subsume the 'M' extension -fself-test: 8412281 pass(es) in 0.647173 seconds Fix by disabling MASK_DIV if multiplication is not available and -mdiv option has not been explicitly passed. Tested the above RV32EC-only toolchain using the GNU simulator: === gcc Summary === # of expected passes 211635 # of unexpected failures 3004 # of expected failures 1061 # of unresolved testcases 5651 # of unsupported tests 18958 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_override_options_internal): Set division option's default to disabled if multiplication is not available. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>	2024-11-19 19:08:15 +02:00
Andreas Schwab	ceddd28d41	testsuite: robustify gcc.target/m68k/20100512-1.c This has been failing since r5-2883-g8cb65b3725f0c3 which caused the memset to be optimized out. Add an unoptimizable reference to the local variable to keep it. * gcc.target/m68k/20100512-1.c (doTest1, doTest2): Add asm that references foo.	2024-11-19 17:38:27 +01:00
Mikael Morin	f74f52642f	fortran: Inline MINLOC/MAXLOC with DIM and scalar MASK [PR90608] Enable the generation of inline code for MINLOC/MAXLOC when argument ARRAY is of integral type and has rank > 1, DIM is a constant, and MASK is scalar (only absent MASK or rank 1 ARRAY were inlined before). Scalar masks are implemented with a wrapping condition around the code one would generate if MASK wasn't present, so they are easy to support once inline code without MASK is working. With this change, there are both expressions evaluated inside the nested loop (ARRAY, and in the future MASK if non-scalar) and expressions evaluated outside of it (MASK if scalar). For both one has to advance the scalarization chain passed as argument SE to gfc_conv_intrinsic_minmaxloc as they are evaluated, but for expressions evaluated from within the nested loop one has to advance additionally the nested scalarization chain of the reduction loop. This is normally handled transparently through the inheritance that is defined when initializing gfc_se structs, but there has to be some variable to inherit from, and there is a single one, SE. This variable is kept as base for out of nested loop expressions only (i.e. for scalar MASK), and this change introduces a new variable to hold the current advance of the nested loop scalarization chain and serve as inheritance base to evaluate nested loop expressions (just ARRAY for now, additionally non-scalar MASK later). PR fortran/90608 gcc/fortran/ChangeLog: * trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Return TRUE if MASK is scalar. (walk_inline_intrinsic_minmaxloc): Append to the scalarization chain a scalar element for MASK if it's present. (gfc_conv_intrinsic_minmaxloc): Use a local gfc_se struct to serve as base for all the expressions evaluated in the nested loop. To evaluate MASK when there is a nested loop, enable usage of the scalarizer and set the original passed in SE argument as current scalarization chain element to use. And use the nested loop from the scalarizer instead of the local loop in that case. gcc/testsuite/ChangeLog: * gfortran.dg/maxloc_bounds_8.f90: Accept the error message generated by the scalarizer in case the MAXLOC intrinsic call is implemented through inline code. * gfortran.dg/minmaxloc_20.f90: New test.	2024-11-19 17:31:25 +01:00
Jason Merrill	b111b55f5b	libstdc++: remove JSON comment. Standard JSON doesn't have comments, and it seems this file needs to be conforming, not the common JSON-with-comments dialect. libstdc++-v3/ChangeLog: * src/c++23/libstdc++.modules.json.in: Remove C++ comment.	2024-11-19 15:36:53 +01:00
Jason Merrill	59fbdb3a87	c++: reduce redundant deprecated warnings If a template uses a deprecated function, we should warn there and not also whenever the template is instantiated. I implement this by suppressing the warning at the location; then to make this also work with modules, I need to make sure to set TREE_NO_WARNING so that the warning spec for this location gets recorded. And then I noticed that has_warning_spec was broken such that if it returned true than get_nowarn_spec would always return null. gcc/cp/ChangeLog: * decl2.cc (cp_handle_deprecated_or_unavailable): Avoid redundant warning. * call.cc (build_over_call): Set TREE_NO_WARNING for calls to deprecated functions. * semantics.cc (finish_call_expr): Propagate TREE_NO_WARNING. gcc/ChangeLog: * warning-control.cc (has_warning_spec): Fix handling of get_no_warning_bit. gcc/testsuite/ChangeLog: * g++.dg/warn/deprecated-21.C: New test. * g++.dg/modules/warn-spec-2_a.C: New test. * g++.dg/modules/warn-spec-2_b.C: New test.	2024-11-19 15:36:27 +01:00
Georg-Johann Lay	a4842917dc	AVR: ad target/84211 - Fix a build failure on some hosts. This fixes a build failure on hosts where HARD_REG_SET is not a scalar. The issue was introduced with the patch for PR84211 in r15-5415. PR target/84211 gcc/ * config/avr/avr-passes.cc (memento_t::apply_insn1): Don't use operator &= on memento_t.known but on memento_t itself.	2024-11-19 15:18:22 +01:00
Andrew Stubbs	234da38a0e	amdgcn: Fix build failure (PR117657) The last patch did the right thing to the wrong parameter, which caused a build failure in Newlib. This patch fixes it. gcc/ChangeLog: PR target/117657 * config/gcn/gcn-valu.md (mask_gather_load<mode><vnsi>): Fix bug in maskload else patch.	2024-11-19 13:53:01 +00:00
Evgeny Karpov	6c11f24532	aarch64: Bypass hidden attribute warnings in MinGW The patch bypasses hidden attribute warnings in MinGW until it is implemented. libgcc/ChangeLog: * config.host: Update. * config/aarch64/t-mingw: New.	2024-11-19 14:27:33 +01:00
Evgeny Karpov	961c504109	Add LTO support The patch reuses the configuration for LTO from ix86 and adds the aarch64 architecture to the list of supported COFF headers. gcc/ChangeLog: * config/aarch64/cygming.h (TARGET_ASM_LTO_START): New. (TARGET_ASM_LTO_END): Likewise. * config/i386/cygming.h (TARGET_ASM_LTO_START): Update. (TARGET_ASM_LTO_END): Likewise. * config/i386/i386-protos.h (i386_pe_asm_lto_start): Delete. (i386_pe_asm_lto_end): Likewise. * config/mingw/winnt.cc (i386_pe_asm_lto_start): Rename into ... (mingw_pe_asm_lto_start): ... this. (i386_pe_asm_lto_end): Rename into ... (mingw_pe_asm_lto_end): ... this. * config/mingw/winnt.h (mingw_pe_asm_lto_start): New. (mingw_pe_asm_lto_end): Likewise. libiberty/ChangeLog: * simple-object-coff.c: Add aarch64.	2024-11-19 14:27:33 +01:00
Evgeny Karpov	55788176f1	aarch64: Extend the offset limit in "symbol + offset" from 1MB to 16MB This patch allows using an offset of up to 16MB in "symbol + offset", instead of 1MB limit that was used previously. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_load_symref_appropriately): Update.	2024-11-19 14:27:33 +01:00
Evgeny Karpov	71381ecc1e	aarch64: Multiple adjustments to support the SMALL code model correctly LOCAL_LABEL_PREFIX has been changed to help the assembly compiler recognize local labels. Emitting locals has been replaced with the .lcomm directive to declare uninitialized data without defining an exact section. Functions and objects were missing declarations. Binutils was not able to distinguish static from external, or an object from a function. mingw_pe_declare_object_type has been added to have type information for relocation on AArch64, which is not the case for ix86. This fix relies on changes in binutils. aarch64: Relocation fixes and LTO https://sourceware.org/pipermail/binutils/2024-August/136481.html gcc/ChangeLog: * config/aarch64/aarch64-coff.h (LOCAL_LABEL_PREFIX): Use "." as the local label prefix. (ASM_OUTPUT_ALIGNED_LOCAL): Remove. (ASM_OUTPUT_LOCAL): New. * config/aarch64/cygming.h (ASM_OUTPUT_EXTERNAL_LIBCALL): Update. (ASM_DECLARE_OBJECT_NAME): New. (ASM_DECLARE_FUNCTION_NAME): New. * config/i386/cygming.h (ASM_DECLARE_COLD_FUNCTION_NAME): Update. (ASM_OUTPUT_EXTERNAL_LIBCALL): Update. * config/mingw/winnt.cc (mingw_pe_declare_function_type): Rename into ... (mingw_pe_declare_type): ... this. (i386_pe_start_function): Update. * config/mingw/winnt.h (mingw_pe_declare_function_type): Rename into ... (mingw_pe_declare_type): ... this.	2024-11-19 14:27:33 +01:00
Evgeny Karpov	fef211ff73	aarch64: Exclude symbols using GOT from code models Symbols using GOT are not supported by the aarch64-w64-mingw32 target and should be excluded from the code models. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_classify_symbol): Disable GOT for PECOFF target.	2024-11-19 14:27:33 +01:00
Evgeny Karpov	e39e523c84	aarch64: Add minimal C++ support The patch resolves compilation issues for the C++ language. Previous patch series contributed to C++ as well, however, C++ could not be tested until we got a C++ compiler and could build at least a "Hello World" C++ program, and in reality, more than that. Another issue has been fixed in the libstdc++ patch. https://gcc.gnu.org/pipermail/libstdc++/2024-September/059472.html gcc/ChangeLog: * config.gcc: Add missing dependencies.	2024-11-19 14:27:33 +01:00

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