sqrt should be 0.5ulp precise, but the current implementation is less
precise than that.
The following patch uses the soft-fp code (like e.g. glibc for x86) for it
if possible. I didn't want to replicate the libgcc infrastructure for
choosing the right sfp-machine.h, so the patch just uses a single generic
implementation. As the code is used solely for the finite positive arguments,
it shouldn't generate NaNs (so the exact form of canonical QNaN/SNaN is
irrelevant), and sqrt for these shouldn't produce underflows/overflows either,
for < 1.0 arguments it always returns larger values than the argument and for
> 1.0 smaller values than the argument.
2024-04-09 Jakub Jelinek <jakub@redhat.com>
PR libquadmath/114623
* sfp-machine.h: New file.
* math/sqrtq.c: Include from libgcc/soft-fp also soft-fp.h and quad.h
if possible.
(USE_SOFT_FP): Define in that case.
(sqrtq): Use soft-fp based implementation for the finite positive
arguments if possible.
Define __APX_INLINE_ASM_USE_GPR32__ for -mapx-inline-asm-use-gpr32.
When __APX_INLINE_ASM_USE_GPR32__ is defined, inline asm statements
should contain only instructions compatible with r16-r31.
gcc/
PR target/114587
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__APX_INLINE_ASM_USE_GPR32__ for -mapx-inline-asm-use-gpr32.
gcc/testsuite/
PR target/114587
* gcc.target/i386/apx-3.c: Likewise.
As PR114614 shows, the newly added test case gcov-20.c by
commit r14-9789-g08a52331803f66 failed on targets which do
not support atomic profile update, there would be a message
like:
warning: target does not support atomic profile update,
single mode is selected
Since the test case adopts -fprofile-update=atomic, it
requires effective target check profile_update_atomic, this
patch is to add the check accordingly.
PR testsuite/114614
gcc/testsuite/ChangeLog:
* gcc.misc-tests/gcov-20.c: Add effective target check
profile_update_atomic.
As the comments in PR88309 show, there are two oversights
in rs6000_gimple_fold_builtin that pass align in bytes to
build_aligned_type but which actually requires align in
bits, it causes unexpected ICE or hanging in function
is_miss_rate_acceptable due to zero align_unit value.
This patch is to fix them by converting bytes to bits, add
an assertion on positive align_unit value and notes function
build_aligned_type requires align measured in bits in its
function comment.
PR target/88309
Co-authored-by: Andrew Pinski <quic_apinski@quicinc.com>
gcc/ChangeLog:
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Fix
wrong align passed to function build_aligned_type.
* tree-ssa-loop-prefetch.cc (is_miss_rate_acceptable): Add an
assertion to ensure align_unit should be positive.
* tree.cc (build_qualified_type): Update function comments.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr88309.c: New test.
This patch fixes the default behavior of cc1gm2 to the description in
the documentation. By default cc1gm2 will allow C preprocessor
directives (they can be turned off via -fno-cpp).
gcc/m2/ChangeLog:
PR modula2/114648
* gm2-compiler/M2Options.mod (LineDirectives): Initially
set to true.
gcc/testsuite/ChangeLog:
PR modula2/114648
* gm2/cpp/default/pass/AdvParse.def: New test.
* gm2/cpp/default/pass/AdvParse.mod: New test.
* gm2/cpp/default/pass/cpp-default-pass.exp: New test.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
The compiler, configured with --enable-checking=yes,rtl,extra ICEs with:
internal compiler error: RTL check: expected elt 0 type 'e' or 'u', have 'E' (rtx unspec) in try_combine, at combine.cc:3237
This is
3236 /* Just replace the CC reg with a new mode. */
3237 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3238 undobuf.other_insn = cc_use_insn;
in combine.cc, where *cc_use_loc is
(unspec:DI [
(reg:CC 17 flags)
] UNSPEC_PUSHFL)
combine assumes CC must be used inside of a comparison and uses XEXP (..., 0)
without checking on the RTX type of the argument.
Replace cc_use_loc with the entire new RTX only in case cc_use_loc satisfies
COMPARISON_P predicate. Otherwise scan the entire cc_use_loc RTX for CC reg
to be updated with a new mode.
PR rtl-optimization/112560
gcc/ChangeLog:
* combine.cc (try_combine): Replace cc_use_loc with the entire
new RTX only in case cc_use_loc satisfies COMPARISON_P predicate.
Otherwise scan the entire cc_use_loc RTX for CC reg to be updated
with a new mode.
* config/i386/i386.md (@pushf<mode>2): Allow all CC modes for
operand 1.
After commit e16f90be2d
"testsuite: Fix up lra effective target", we get for nvptx target:
-PASS: gcc.c-torture/compile/asmgoto-2.c -O0 (test for excess errors)
+ERROR: gcc.c-torture/compile/asmgoto-2.c -O0 : no files matched glob pattern "lra1020113.c.[0-9][0-9][0-9]r.reload" for " dg-do 2 compile { target lra } "
Etc.
However, nvptx appears to support 'asm goto' with outputs, including the
new execution test case:
PASS: gcc.dg/pr107385.c execution test
Therefore, generally use new effective-target 'asm_goto_with_outputs' instead
of 'lra'. One exceptions is 'gcc.dg/pr110079.c', which doesn't use 'asm goto'
with outputs, and continues using effective-target 'lra', with special-casing
nvptx target, to avoid ERROR for 'lra'.
gcc/
* doc/sourcebuild.texi (Effective-Target Keywords): Document
'asm_goto_with_outputs'. Add comment to 'lra'.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_lra): Add
comment.
(check_effective_target_asm_goto_with_outputs): New.
* gcc.c-torture/compile/asmgoto-2.c: Use it.
* gcc.c-torture/compile/asmgoto-5.c: Likewise.
* gcc.c-torture/compile/asmgoto-6.c: Likewise.
* gcc.c-torture/compile/pr98096.c: Likewise.
* gcc.dg/pr100590.c: Likewise.
* gcc.dg/pr107385.c: Likewise.
* gcc.dg/pr108095.c: Likewise.
* gcc.dg/pr97954.c: Likewise.
* gcc.dg/torture/pr100329.c: Likewise.
* gcc.dg/torture/pr100398.c: Likewise.
* gcc.dg/torture/pr100519.c: Likewise.
* gcc.dg/torture/pr110422.c: Likewise.
* gcc.dg/pr110079.c: Special-case nvptx target.
Currently, we silently disable libgomp GCN and nvptx plugins/devices in
presence of certain error conditions during device probing, thus typically
silently resorting to host-fallback execution. Make such errors fatal, similar
as for any other device access later on, so that we early and reliably notice
when things go wrong. (Keep just two cases non-fatal: (a) libgomp GCN or nvptx
plugins are available but 'libhsa-runtime64.so.1' or 'libcuda.so.1' are not,
and (b) those are available, but the corresponding devices are not.)
This resolves the issue that we've got execution test cases unexpectedly
PASSing, despite:
libgomp: GCN fatal error: Run-time could not be initialized
Runtime message: HSA_STATUS_ERROR_OUT_OF_RESOURCES: The runtime failed to allocate the necessary resources. This error may also occur when the core runtime library needs to spawn threads or create internal OS-specific events.
..., and therefore they were not offloaded to the GCN device, but ran in
host-fallback execution mode. What happend in that scenario is that in
'init_hsa_context' during the initial 'GOMP_OFFLOAD_get_num_devices' we ran
into 'HSA_STATUS_ERROR_OUT_OF_RESOURCES', but it wasn't fatal, but just
silently disabled the libgomp plugin/device.
Especially "entertaining" were cases where such unintended host-fallback
execution happened during effective-target checks like
'offload_device_available' (host-fallback execution there meaning: no offload
device available), but actual test cases then were running with an offload
device available, and therefore mis-configured.
include/
* cuda/cuda.h (CUresult): Add 'CUDA_ERROR_NO_DEVICE'.
libgomp/
* plugin/plugin-gcn.c (init_hsa_context): Add and handle
'bool probe' parameter. Adjust all users; errors during device
probing are fatal.
* plugin/plugin-nvptx.c (nvptx_get_num_devices): Aside from
'CUDA_ERROR_NO_DEVICE', errors during device probing are fatal.
This fixes a side-effect of/regression caused by r14-9822-g93adf88cc6744a,
which was for the same PR.
PR libfortran/114304
libgfortran/ChangeLog:
* io/list_read.c (eat_separator): Accept tab as alternative to space.
gcc/testsuite/ChangeLog:
* gfortran.dg/pr114304-2.f90: New test.
PR 113359 shows that (at least with -fno-strict-aliasing) ICF can
unify two functions which copy an aggregate type of the same size but
then SRA, through its total scalarization, can copy the aggregate by
pieces, skipping paddding, but the padding was not the same in the two
original functions that ICF unified.
This patch enhances SRA with the ability to collect padding
information which then can be compared from within ICF. Unfortunately
SRA uses OPTION_SET_P when determining its limits, so ICF needs to
switch cfuns at least once to figure it out too.
gcc/ChangeLog:
2024-03-27 Martin Jambor <mjambor@suse.cz>
PR ipa/113359
* ipa-icf-gimple.h (func_checker): New members
safe_for_total_scalarization_p, m_total_scalarization_limit_known_p
and m_total_scalarization_limit.
(func_checker::func_checker): Initialize new member variables.
* ipa-icf-gimple.cc: Include tree-sra.h.
(func_checker::func_checker): Initialize new member variables.
(func_checker::safe_for_total_scalarization_p): New function.
(func_checker::compare_operand): Use the new function.
* tree-sra.h (sra_get_max_scalarization_size): Declare.
(sra_total_scalarization_would_copy_same_data_p): Likewise.
* tree-sra.cc (prepare_iteration_over_array_elts): New function.
(class sra_padding_collecting): New.
(sra_padding_collecting::record_padding): Likewise.
(scalarizable_type_p): Rename to totally_scalarizable_type_p. Add
ability to record padding when requested.
(totally_scalarize_subtree): Split out gathering information necessary
to iterate over array elements to prepare_iteration_over_array_elts.
Fix errornous early exit.
(analyze_all_variable_accesses): Adjust the call to
totally_scalarizable_type_p. Move determining of total scalariation
size limit...
(sra_get_max_scalarization_size): ...here.
(check_ts_and_push_padding_to_vec): New function.
(sra_total_scalarization_would_copy_same_data_p): Likewise.
gcc/testsuite/ChangeLog:
2024-03-27 Martin Jambor <mjambor@suse.cz>
PR ipa/113359
* gcc.dg/lto/pr113359-1_0.c: New.
* gcc.dg/lto/pr113359-1_1.c: Likewise.
* gcc.dg/lto/pr113359-2_0.c: Likewise.
* gcc.dg/lto/pr113359-2_1.c: Likewise.
* gcc.dg/lto/pr113359-3_0.c: Likewise.
* gcc.dg/lto/pr113359-3_1.c: Likewise.
* gcc.dg/lto/pr113359-4_0.c: Likewise.
* gcc.dg/lto/pr113359-4_1.c: Likewise.
* gcc.dg/lto/pr113359-5_0.c: Likewise.
* gcc.dg/lto/pr113359-5_1.c: Likewise.
In PR 113907 comment #58, Honza found a case where ICF thinks bodies
of functions are equivalent but becaise of difference in aliases in a
memory access, different aggregate jump functions are associated with
supposedly equivalent call statements. This patch adds a way to
compare jump functions and plugs it into ICF to avoid the issue.
gcc/ChangeLog:
2024-03-20 Martin Jambor <mjambor@suse.cz>
PR ipa/113907
* ipa-prop.h (class ipa_vr): Declare new overload of a member function
equal_p.
(ipa_jump_functions_equivalent_p): Declare.
* ipa-prop.cc (ipa_vr::equal_p): New function.
(ipa_agg_pass_through_jf_equivalent_p): Likewise.
(ipa_agg_jump_functions_equivalent_p): Likewise.
(ipa_jump_functions_equivalent_p): Likewise.
* ipa-cp.h (values_equal_for_ipcp_p): Declare.
* ipa-cp.cc (values_equal_for_ipcp_p): Make function public.
* ipa-icf-gimple.cc: Include alloc-pool.h, symbol-summary.h, sreal.h,
ipa-cp.h and ipa-prop.h.
(func_checker::compare_gimple_call): Comapre jump functions.
gcc/testsuite/ChangeLog:
2024-03-20 Martin Jambor <mjambor@suse.cz>
PR ipa/113907
* gcc.dg/lto/pr113907_0.c: New.
* gcc.dg/lto/pr113907_1.c: Likewise.
* gcc.dg/lto/pr113907_2.c: Likewise.
Instead of just omitting the definition of __unicode::_Utf8_view when
char8_t is disabled, we can make it use char instead.
libstdc++-v3/ChangeLog:
PR libstdc++/114519
* include/bits/unicode.h (_Utf8_view) [!__cpp_char8_t]: Define
using char instead of char8_t.
* testsuite/ext/unicode/view.cc: Use u8""sv literals to create
string views, instead of std::u8string_view.
Adjust expected errors or skip tests as UNSUPPORTED if -fno-char8_t is
used in the test flags.
libstdc++-v3/ChangeLog:
* testsuite/20_util/integer_comparisons/equal_neg.cc: Use
no-opts selector for errors that depend on -fchar8_t.
* testsuite/20_util/integer_comparisons/greater_equal_neg.cc:
Likewise.
* testsuite/20_util/integer_comparisons/greater_neg.cc:
Likewise.
* testsuite/20_util/integer_comparisons/in_range_neg.cc:
Likewise.
* testsuite/20_util/integer_comparisons/less_equal_neg.cc:
Likewise.
* testsuite/20_util/integer_comparisons/less_neg.cc: Likewise.
* testsuite/20_util/integer_comparisons/not_equal_neg.cc:
Likewise.
* testsuite/21_strings/basic_string/hash/hash_char8_t.cc: Skip
if -fno-char8_t is used.
* testsuite/21_strings/headers/cuchar/functions_std_cxx20.cc:
Likewise.
* testsuite/27_io/basic_ostream/inserters_character/char/deleted.cc:
Likewise.
* testsuite/27_io/basic_ostream/inserters_character/wchar_t/deleted.cc:
Likewise.
* testsuite/27_io/filesystem/path/factory/u8path-depr.cc: Use
char for u8 literal if char8_t is not available.
* testsuite/27_io/headers/iosfwd/synopsis.cc: Check
__cpp_char8_t.
* testsuite/29_atomics/atomic_integral/wait_notify.cc: Likewise.
* testsuite/29_atomics/headers/atomic/types_std_c++20_neg.cc:
Remove check for _GLIBCXX_USE_CHAR8_T.
We don't need separate tests for the C++17 and C++20 cases, we can just
have one test that uses __cpp_char8_t to adjust whether it tests char8_t
or not. This means the C++20 one doesn't fail if -fno-char8_t is used.
libstdc++-v3/ChangeLog:
* testsuite/20_util/from_chars/1_neg.cc: Add char8_t cases,
using a struct of that name if -fno-char8_t is active.
* testsuite/20_util/from_chars/1_c++20_neg.cc: Removed.
Not sure how this happend, but: svsudot is supposed to be expanded
as USDOT with the operands swapped. However, a thinko in the
expansion of svsudot meant that the arguments weren't in fact
swapped; the attempted swap was just a no-op. And the testcases
blithely accepted that.
gcc/
PR target/114607
* config/aarch64/aarch64-sve-builtins-base.cc
(svusdot_impl::expand): Fix botched attempt to swap the operands
for svsudot.
gcc/testsuite/
PR target/114607
* gcc.target/aarch64/sve/acle/asm/sudot_s32.c: New test.
This implements TLS Descriptors (TLSDESC) as specified in [1].
The 4-instruction sequence is implemented as a single RTX insn for
simplicity, but this can be revisited later if instruction scheduling or
more flexible RA is desired.
The default remains to be the traditional TLS model, but can be configured
with --with-tls={trad,desc}. The choice can be revisited once toolchain
and libc support ships.
[1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373.
gcc/ChangeLog:
* config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor.
* config.gcc: Add --with-tls configuration option to change the
default TLS flavor.
* config/riscv/riscv.h: Add TARGET_TLSDESC determined from
-mtls-dialect and with_tls defaults.
* config/riscv/riscv-opts.h: Define enum riscv_tls_type for the
two TLS flavors.
* config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type.
* config/riscv/riscv.md: Add instruction sequence for TLSDESC.
* config/riscv/riscv.cc (riscv_symbol_insns): Add instruction
sequence length data for TLSDESC.
(riscv_legitimize_tls_address): Add lowering of TLSDESC.
* doc/install.texi: Document --with-tls for RISC-V.
* doc/invoke.texi: Document -mtls-dialect for RISC-V.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/tls_1.x: Add TLSDESC GD test case.
* gcc.target/riscv/tlsdesc.c: Same as above.
The following testcase is miscompiled, because we have initially
a movti which loads the 0x3f8000003f800000ULL TImode constant
from constant pool. Later on we split it into a pair of DImode
loads. Now, for the first load (why just that?, though not stage4
material) we trigger the peephole2 which uses s390_const_int_pool_entry_p.
That function doesn't check at all the constant pool mode though, sees
the constant pool at that address has a CONST_INT value and just assumes
that is the value to return, which is especially wrong for big-endian,
if it is a DImode load from offset 0, it should be loading 0 rather than
0x3f8000003f800000ULL.
The following patch adds checks if we are extracing a MODE_INT mode,
if the constant pool has MODE_INT mode as well, punts if constant pool
has smaller mode size than the extraction one (then it would be UB),
if it has the same mode as before keeps using what it did before,
if constant pool has a larger mode than the one being extracted, uses
simplify_subreg. I'd have used avoid_constant_pool_reference
instead which can handle also offsets into the constant pool constants,
but it can't handle UNSPEC_LTREF.
Another thing is that once that is fixed, we ICE when we extract constant
like 0, ior insn predicate require non-0 constant. So, the patch also
fixes the peephole2 so that if either 32-bit half is zero, it uses a mere
load of the constant into register rather than a pair of such load and ior.
2024-04-08 Jakub Jelinek <jakub@redhat.com>
PR target/114605
* config/s390/s390.cc (s390_const_int_pool_entry_p): Punt
if mem doesn't have MODE_INT mode, or pool constant doesn't
have MODE_INT mode, or if pool constant mode is smaller than
mem mode. If mem mode is different from pool constant mode,
try to simplify subreg. If that doesn't work, punt, if it
does, use the simplified constant instead of the constant pool
constant.
* config/s390/s390.md (movdi from const pool peephole): If
either low or high 32-bit part is zero, just emit move insn
instead of move + ior.
* gcc.dg/pr114605.c: New test.
The test for this intrinsic was failing silently and so it failed to
report the bug reported in 114521. This patch modifes the test to
report the result.
Bug report: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114521
Signed-off-by: Jonathan Swinney <jswinney@amazon.com>
gcc/testsuite/
* gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: Exit with a nonzero
code if the test fails.
This commit unfortunately added explanation to the git revert generated
message, breaking ChangeLog generation.
2024-04-08 Jakub Jelinek <jakub@redhat.com>
* gcc-changelog/git_update_version.py: Add
8057f9aa1f to IGNORED_COMMITS.
We're inspecting the replaced PHI node after releasing it.
PR tree-optimization/114624
* tree-scalar-evolution.cc (final_value_replacement_loop):
Get at the PHI arg location before releasing the PHI node.
* gcc.dg/torture/pr114624.c: New testcase.
The RVV intrinisc API has sorts of required extension from both
the march or target attribute. It will have error message similar
to below:
built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension
However, it is not accurate as we have many additional sub extenstion
besides v extension. For example, zvbb, zvbk, zvbc ... etc. This patch
would like to refine the error message with a friendly hint for the
required extension. For example as below:
vuint64m1_t
__attribute__((target("arch=+v")))
test_1 (vuint64m1_t op_1, vuint64m1_t op_2, size_t vl)
{
return __riscv_vclmul_vv_u64m1 (op_1, op_2, vl);
}
When compile with march=rv64gc and target arch=+v, we will have error
message as below:
error: built-in function '__riscv_vclmul_vv_u64m1(op_1, op_2, vl)'
requires the 'zvbc' ISA extension
Then the end-user will get the point that the *zvbc* extension is missing
for the intrinisc API easily.
The below tests are passed for this patch.
* The riscv fully regression tests.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (build_one): Pass
required_ext arg when invoke add function.
(build_th_loadstore): Ditto.
(struct vcreate_def): Ditto.
(struct read_vl_def): Ditto.
(struct vlenb_def): Ditto.
* config/riscv/riscv-vector-builtins.cc (function_builder::add_function):
Introduce new arg required_ext to fill in the register func.
(function_builder::add_unique_function): Ditto.
(function_builder::add_overloaded_function): Ditto.
(expand_builtin): Leverage required_extensions_specified to
check if the required extension is provided.
* config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name): New
func impl to convert the required_ext enum to the extension name.
(required_extensions_specified): New func impl to predicate if
the required extension is well feeded.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c: Adjust
the error message for v extension.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c: Ditto.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-1.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-10.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-2.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-3.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-4.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-5.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-6.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-7.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-8.c: New test.
* gcc.target/riscv/rvv/base/intrinsic_required_ext-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
The specs for coverage ere out of date leading to test fails for
fcondition-coverage cases. Fixed by updating to match the specs
in gcc/gcc.cc.
gcc/ChangeLog:
* config/darwin.h (LINK_COMMAND_SPEC_A): Update coverage
specs.
Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
The program points start from 1, so max_point should be equal to
length().
Tested on RV64 and no regression.
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc: Use length()
Signed-off-by: demin.han <demin.han@starfivetech.com>
In previous, we allowed the target(("arch=+v")) for a function with
rv64gc build. This patch would like to support more arch options as
below:
* zve32x
* zve32f
* zve64x
* zve64f
* zve64d
* zvfhmin
* zvfh
* zvk*
* zvbb
For example, we have sample code as below.
vfloat32m1_t
__attribute__((target("arch=+zve64f")))
test_9 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
{
return __riscv_vfadd_vv_f32m1 (a, b, vl);
}
It will generate the asm code when build with -O3 -march=rv64gc
test_9:
vsetvli zero,a0,e32,m1,ta,ma
vfadd.vv v8,v8,v9
ret
Meanwhile, this patch introduces more error handling for the target
attribute. Take arch=+zve32x with vfloat32m1_t will have error message
"'vfloat32m1_t' requires the zve32f, zve64f or zve64d ISA extension".
And take arch=+zve32f with vfloat16m1_t will have error message
"'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension".
By default, all the RVV types includes the cmdline march will be
registered when include the riscv_vector.h. And we have sorts of check
during args and return types.
Below test are passed for this patch:
* The riscv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): New
struct to hold all intrinisc related flags.
(riscv_pragma_intrinsic_flags_pollute): New func to pollute
the intrinsic flags and backup original flags.
(riscv_pragma_intrinsic_flags_restore): New func to restore
the flags from the backup intrinsic flags.
(riscv_pragma_intrinsic): Pollute the flags and register all
possible builtin types and functions, then restore and reinit.
* config/riscv/riscv-protos.h (reinit_builtins): New func
decl to reinit after flags pollution.
(riscv_option_override): New extern func decl.
* config/riscv/riscv-vector-builtins.cc (register_builtin_types_on_null):
New func to register builtin types if null.
(DEF_RVV_TYPE): Ditto.
(DEF_RVV_TUPLE_TYPE): Ditto.
(reinit_builtins): New func impl to reinit after flags pollution.
(expand_builtin): Return
target rtx after error_at.
* config/riscv/riscv.cc (riscv_vector_int_type_p): New predicate
func to tell one tree type is integer or not.
(riscv_vector_float_type_p): New predicate func to tell one tree
type is float or not.
(riscv_vector_element_bitsize): New func to get the element bitsize
of a vector tree type.
(riscv_vector_required_min_vlen): New func to get the required min vlen
of a vector tree type.
(riscv_validate_vector_type): New func to validate the tree type
is valid on flags.
(riscv_return_value_is_vector_type_p): Leverage the func
riscv_validate_vector_type to do the tree type validation.
(riscv_arguments_is_vector_type_p): Ditto.
(riscv_override_options_internal): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr109479-1.c: Adjust the existing test
scenarios and add new error check tests.
* gcc.target/riscv/rvv/base/pr109479-2.c: Ditto.
* gcc.target/riscv/rvv/base/pr109479-3.c: Ditto.
* gcc.target/riscv/rvv/base/pr109479-4.c: Diito.
* gcc.target/riscv/rvv/base/pr109479-5.c: Diito.
* gcc.target/riscv/rvv/base/pr109479-6.c: Diito.
* gcc.target/riscv/rvv/base/user-10.c: Ditto.
* gcc.target/riscv/rvv/base/user-12.c: Ditto.
* gcc.target/riscv/rvv/base/user-13.c: Ditto.
* gcc.target/riscv/rvv/base/user-14.c: Ditto.
* gcc.target/riscv/rvv/base/user-15.c: Ditto.
* gcc.target/riscv/rvv/base/user-2.c: Ditto.
* gcc.target/riscv/rvv/base/user-3.c: Ditto.
* gcc.target/riscv/rvv/base/user-5.c: Ditto.
* gcc.target/riscv/rvv/base/user-6.c: Ditto.
* gcc.target/riscv/rvv/base/user-9.c: Ditto.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-30.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-31.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-32.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-33.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-34.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-35.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-36.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-37.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-38.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-40.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-41.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-47.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-48.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-49.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-50.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-51.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-52.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-53.c: New test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Xi Ruoyao set the alignment rules under LA464 in commit r14-1839,
but the macro ASM_OUTPUT_ALIGN_WITH_NOP was removed in R14-4674,
which affected the alignment rules.
So I set different aligns on LA464 and LA664 again to test the
performance of spec2006, and modify the alignment based on the test
results.
gcc/ChangeLog:
PR target/112919
* config/loongarch/loongarch-def.cc (la664_align): Newly defined
function that sets alignment rules under the LA664 microarchitecture.
* config/loongarch/loongarch-opts.cc
(loongarch_target_option_override): If not optimizing for size, set
the default alignment to what the target wants.
* config/loongarch/loongarch-tune.h (struct loongarch_align): Add
new member variables jump and loop.
This patch allows cc1gm2 to resolve constant expressions which use
relative operators. Previous to the patch the result of a relop
was stored in a temporary variable set by an if then else quadruple
sequence. This patch marks a const expression in the quadruples
and then reduces this sequence of quadruples into a single
assignment to an internal constant.
gcc/m2/ChangeLog:
PR modula2/114617
* gm2-compiler/M2GenGCC.mod (CodeStatememt): Add quad trace.
(ResolveConstantExpressions): Add parameter p to FoldIfLess,
FoldIfGre, FoldIfLessEqu, FoldIfGreEqu, FoldIfEqu, FoldIfNotEqu,
FoldIfIn and FoldIfNotIn.
(CodeInline): Add constExpr variable and pass it to GetQuadOtok.
(CodeReturnValue): Ditto.
(CodeParam): Ditto.
(FoldStringLength): Ditto.
(FoldStringConvertM2nul): Ditto.
(FoldStringConvertCnul): Ditto.
(DeclaredOperandsBecomes): Ditto.
(TypeCheckBecomes): Ditto.
(PerformFoldBecomes): Ditto.
(CodeBecomes): Ditto.
(CheckElementSetTypes): Ditto.
(CodeBinarySet): Ditto.
(PerformCodeIfLess): Ditto.
(PerformCodeIfGre): Ditto.
(PerformCodeIfLessEqu): Ditto.
(PerformCodeIfGreEqu): Ditto.
(PerformCodeIfEqu): Ditto.
(PerformCodeIfNotEqu): Ditto.
(IsValidExpressionRelOp): Ditto.
(PerformCodeIfIn): Ditto.
(PerformCodeIfNotIn): Ditto.
(CodeXIndr): Ditto.
(QuadCondition): New procedure function.
(IsBooleanRelOpPattern): Ditto.
(FoldBooleanRelopPattern): Ditto.
(FoldIfGre): Check for boolean relop constant expression and
add parameter p.
(FoldIfLessEqu): Ditto.
(FoldIfIn): Ditto.
(FoldIfEqu): Ditto.
(FoldIfNotIn): Ditto.
(FoldIfGreEqu): New procedure.
(FoldIfNotEqu): Ditto.
* gm2-compiler/M2Optimize.mod (ReduceBranch): Add constExpr
variable and pass it to GetQuadOtok.
* gm2-compiler/M2Quads.def (IsBecomes): New procedure function.
(IsDummy): Ditto.
(IsQuadConstExpr): Ditto.
(SetQuadConstExpr): Ditto.
(GetQuadDest): New procedure.
(GetQuadOp1): New procedure.
(GetQuadOp2): New procedure.
(GetQuadOp3): New procedure.
(GetQuadOtok): New procedure.
(GetQuadOTypetok): New procedure.
(PutQuadOtok): New procedure.
(IsInConstParameters): New procedure function.
* gm2-compiler/M2Quads.mod (IsBecomes): New procedure function.
(IsDummy): Ditto.
(IsQuadConstExpr): Ditto.
(SetQuadConstExpr): Ditto.
(GetQuadDest): New procedure.
(GetQuadOp1): New procedure.
(GetQuadOp2): New procedure.
(GetQuadOp3): New procedure.
(GetQuadOtok): New procedure.
(GetQuadOTypetok): New procedure.
(PutQuadOtok): New procedure.
(IsInConstParameters): New procedure function.
(ConstStack): Remove to ...
(ConstExprStack): ... this.
(ConstParamStack): New variable and initialize.
(QuadFrame): New field ConstExpr.
(GetQuadOtok): Add parameter constExpr and assign.
(PutQuadOtok): Add constExpr parameter and assign.
(PutQuadOType): Ditto.
(GetQuadOTypetok): Ditto.
(EraseQuad): Assign ConstExpr to FALSE.
(FoldSubrange): Set ConstExpr to FALSE in BecomesOp.
(PushInConstParameters): New procedure.
(PopInConstParameters): New procedure.
(IsInConstParameters): New procedure function.
* gm2-compiler/M2SymInit.mod (IssueConditional): Add
constExpr boolean variable.
(CheckReadBeforeInitQuad): Ditto.
(trashParam): Ditto.
* gm2-compiler/P3Build.bnf (ConstExpression): Call
PushInConstExpression and PopInConstExpression.
(ConstSetOrQualidentOrFunction): Call
PushInConstParameters and PopInConstParameters.
* gm2-compiler/PCBuild.bnf (ConstExpression): Call
PushInConstExpression and PopInConstExpression.
* gm2-compiler/PHBuild.bnf: Ditto
* gm2-gcc/m2expr.cc (m2expr_BuildCondIfExpression): New
function.
* gm2-gcc/m2expr.def (BuildCondIfExpression): New prototype.
* gm2-gcc/m2expr.h (m2expr_BuildCondIfExpression): New function.
gcc/testsuite/ChangeLog:
PR modula2/114617
* gm2/iso/const/pass/iso-const-pass.exp: New test.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
PR libfortran/114304
PR libfortran/105473
libgfortran/ChangeLog:
* io/list_read.c (eat_separator): Add logic to handle spaces
preceding a comma or semicolon such that that a 'null' read
occurs without error at the end of comma or semicolon
terminated input lines. Add check and error message for ';'.
(list_formatted_read_scalar): Treat comma as a decimal point
when specified by the decimal mode on the first item.
gcc/testsuite/ChangeLog:
* gfortran.dg/pr105473.f90: Modify to verify new error message.
* gfortran.dg/pr114304.f90: New test.
Don't use implicit shift count in double-precision shifts in AT&T syntax
since they aren't in Intel SDM. Keep the 's' modifier for backward
compatibility with inline asm statements.
PR target/114590
* config/i386/i386.md (x86_64_shld): Use explicit shift count in
AT&T syntax.
(x86_64_shld_ndd): Likewise.
(x86_shld): Likewise.
(x86_shld_ndd): Likewise.
(x86_64_shrd): Likewise.
(x86_64_shrd_ndd): Likewise.
(x86_shrd): Likewise.
(x86_shrd_ndd): Likewise.
When a function is tree-inlined, copy the condition -> expression mapping
from the inlined function into the caller, shifted so uids are not
mixed. Tree inlining was always problematic under condition coverage -
either through a nullptr dereference (triggered by the test case), or
through quietly mixing caller conditions with the callee conditions.
PR middle-end/114599
gcc/ChangeLog:
* tree-inline.cc (add_local_variables): Copy cond_uids mappings.
gcc/testsuite/ChangeLog:
* gcc.misc-tests/gcov-pr114599.c: New test.
The __sigsetjmp test was added as a regression test in an early
iteration of the MC/DC support, as it caused an internal compiler error.
This was triggered by a code path which did not make it through to the
final revision. Since this test really only worked on systems with
__sigsetjmp, and does not serve a purpose any more it can be removed.
gcc/testsuite/ChangeLog:
* gcc.misc-tests/gcov-19.c: Remove test.
gcc/analyzer/ChangeLog:
PR analyzer/114588
* access-diagram.cc (access_diagram_impl::access_diagram_impl):
Replace hardcoded colors for valid_style and invalid_style with
calls to text_art::get_style_from_color_cap_name.
gcc/ChangeLog:
PR analyzer/114588
* diagnostic-color.cc (color_dict): Add "valid" and "invalid" as
color capability names.
* doc/invoke.texi: Document them in description of GCC_COLORS.
* text-art/style.cc: Include "diagnostic-color.h".
(text_art::get_style_from_color_cap_name): New.
* text-art/types.h (get_style_from_color_cap_name): New decl.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
When we have '-O3 -g' we emit a bunch of LB{B,E} local labels which
were not currently being discarded, leading to some test fails.
Fixed by adding this case to the ignored labels.
gcc/testsuite/ChangeLog:
* lib/scanasm.exp: Add 'LB*' to the local labels that are
ignored for Darwin.
Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
Interactions of IPA-CP and IPA-SRA on the same data is a rather big
source of issues, I'm afraid. PR 113964 is a situation where IPA-CP
propagates an unsigned short in a union parameter into a function
which itself calls a different function which has a same union
parameter and both these union parameters are split with IPA-SRA. The
leaf function however uses a signed short member of the union.
In the calling function, we get the unsigned constant as the
replacement for the union and it is then passed in the call without
any type compatibility checks. Apparently on riscv64 it matters
whether the parameter is signed or unsigned short and so the leaf
function can see different values.
Fixed by using useless_type_conversion_p at the appropriate place and
if it fails, use force_value_to type as elsewhere in similar
situations.
gcc/ChangeLog:
2024-04-04 Martin Jambor <mjambor@suse.cz>
PR ipa/113964
* ipa-param-manipulation.cc (ipa_param_adjustments::modify_call):
Force values obtined through pass-through maps to the expected
split type.
gcc/testsuite/ChangeLog:
2024-04-04 Patrick O'Neill <patrick@rivosinc.com>
Martin Jambor <mjambor@suse.cz>
PR ipa/113964
* gcc.dg/ipa/pr114247.c: New test.
The new support for gcov modified condition/decision coverage
introduced two new flags for gcc, -Wcoverage-too-many-conditions and
-fcondition-coverage. But didn't regenerate the gcc/common.opt.urls.
Fixes: 08a5233180 ("Add condition coverage (MC/DC)")
gcc/ChangeLog:
* common.opt.urls: Regenerate.
aarch64-sve.md had a pattern that combined:
cmpeq pb.T, pa/z, zc.T, #0
mov zd.T, pb/z, #1
into:
cnot zd.T, pa/m, zc.T
But this is only valid if pa.T is a ptrue. In other cases, the
original would set inactive elements of zd.T to 0, whereas the
combined form would copy elements from zc.T.
gcc/
PR target/114603
* config/aarch64/aarch64-sve.md (@aarch64_pred_cnot<mode>): Replace
with...
(@aarch64_ptrue_cnot<mode>): ...this, requiring operand 1 to be
a ptrue.
(*cnot<mode>): Require operand 1 to be a ptrue.
* config/aarch64/aarch64-sve-builtins-base.cc (svcnot_impl::expand):
Use aarch64_ptrue_cnot<mode> for _x operations that are predicated
with a ptrue. Represent other _x operations as fully-defined _m
operations.
gcc/testsuite/
PR target/114603
* gcc.target/aarch64/sve/acle/general/cnot_1.c: New test.
The #undef was added in r0-90320-g100d537d7a7b5c but it never did
anything.
gcc/c-family/ChangeLog:
* c-warn.cc (warn_about_parentheses): Remove an #undef.
We evaluate constexpr functions on the original, pre-genericization bodies.
That means that the function body we're evaluating will not have gone
through cp_genericize_r's "Map block scope extern declarations to visible
declarations with the same name and type in outer scopes if any". Here:
constexpr bool bar() { return true; } // #1
constexpr bool foo() {
constexpr bool bar(void); // #2
return bar();
}
it means that we:
1) register_constexpr_fundef (#1)
2) cp_genericize (#1)
nothing interesting happens
3) register_constexpr_fundef (foo)
does copy_fn, so we have two copies of the BIND_EXPR
4) cp_genericize (foo)
this remaps #2 to #1, but only on one copy of the BIND_EXPR
5) retrieve_constexpr_fundef (foo)
we find it, no problem
6) retrieve_constexpr_fundef (#2)
and here #2 isn't found in constexpr_fundef_table, because
we're working on the BIND_EXPR copy where #2 wasn't mapped to #1
so we fail. We've only registered #1.
It should work to use DECL_LOCAL_DECL_ALIAS (which used to be
extern_decl_map). We evaluate constexpr functions on pre-cp_fold
bodies to avoid diagnostic problems, but the remapping I'm proposing
should not interfere with diagnostics.
This is not a problem for a global scope redeclaration; there we go
through duplicate_decls which keeps the DECL_UID:
DECL_UID (olddecl) = olddecl_uid;
and DECL_UID is what constexpr_fundef_hasher::hash uses.
PR c++/111132
gcc/cp/ChangeLog:
* constexpr.cc (get_function_named_in_call): Use
cp_get_fndecl_from_callee.
* cvt.cc (cp_get_fndecl_from_callee): If there's a
DECL_LOCAL_DECL_ALIAS, use it.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/constexpr-redeclaration3.C: New test.
* g++.dg/cpp0x/constexpr-redeclaration4.C: New test.
The following testcase is miscompiled, because in the vectorized
epilogue the vectorizer assumes it can use aligned loads/stores
(if the base decl gets alignment increased), but it actually doesn't
increase that.
This is because r10-4203-g97c1460367 added the hunk following
patch removes. The explanation feels reasonable, but actually it
is not true as the testcase proves.
The thing is, we vectorize the main loop with 64-byte vectors
and the corresponding data refs have base_alignment 16 (the
a array has DECL_ALIGN 128) and offset_alignment 32. Now, because
of the offset_alignment 32 rather than 64, we need to use unaligned
loads/stores in the main loop (and ditto in the first load/store
in vectorized epilogue). But the second load/store in the vectorized
epilogue uses only 32-byte vectors and because it is a multiple
of offset_alignment, it checks if we could increase alignment of the
a VAR_DECL, the function returns true, sets base_misaligned = true
and says the access is then aligned.
But when update_epilogue_loop_vinfo clears base_misaligned with the
assumption that the var had to have the alignment increased already,
the update of DECL_ALIGN doesn't happen anymore.
Now, I'd think this base_alignment = false was needed before
r10-4030-gd2db7f7901 change was committed where it incorrectly
overwrote DECL_ALIGN even if it was already larger, rather than
just always increasing it. But with that change in, it doesn't
make sense to me anymore.
Note, the testcase is latent on the trunk, but reproduces on the 13
branch.
2024-04-05 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/114566
* tree-vect-loop.cc (update_epilogue_loop_vinfo): Don't clear
base_misaligned.
* gcc.target/i386/avx512f-pr114566.c: New test.
m2 has a m2.dvi build rule, but lacks the m2.install-dvi one.
2024-04-04 Christophe Lyon <christophe.lyon@linaro.org>
gcc/m2/
* Make-lang.in (m2.install-dvi): New rule.
With commit 7520a4992c
"nvptx: In mkoffload.cc, call diagnostic_color_init + gcc_init_libintl",
we regressed:
[-PASS:-]{+FAIL:+} libgomp.c/reverse-offload-sm30.c at line 15 (test for warnings, line )
[-PASS:-]{+FAIL:+} libgomp.c/reverse-offload-sm30.c (test for excess errors)
libgomp/
* testsuite/libgomp.c/reverse-offload-sm30.c: Set 'GCC_COLORS' to the empty string.
Seems configure hasn't been regenerated properly after the last
acinclude.m4 change.
2024-04-05 Jakub Jelinek <jakub@redhat.com>
* configure: Regenerate.
