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(attr cpu): Add new cpu types for arm8 and strongarm.
(attr ldsched): New attribute, set if processor has a load_delay slot. (function_unit core): Rework to handle load delay slots. (function_unit loader): New function unit. (movsi): Handle pic. (pic_load_addr): New expand. (*pic_load_addr_based_insn, pic_add_dot_plus_eight): New patterns. (peepholes to cause flow to return to a label after a function call): Delete, these have been disabled for a while now. From-SVN: r14052
This commit is contained in:
Richard Earnshaw
parent
7a80182693
commit
fef37aaf99
@ -1,5 +1,5 @@
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;;- Machine description for Advanced RISC Machines' ARM for GNU compiler
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;; Copyright (C) 1991, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
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;; Copyright (C) 1991, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
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;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
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;; and Martin Simmons (@harleqn.co.uk).
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;; More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
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@ -49,7 +49,7 @@
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; by a call insn: on the arm6 they are if in 32-bit addressing mode; on the
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; arm2 and arm3 the condition codes are restored by the return.
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(define_attr "cpu" "arm2,arm3,arm6,arm7"
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(define_attr "cpu" "arm2,arm3,arm6,arm7,arm8,st_arm"
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(const (symbol_ref "arm_cpu_attr")))
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; Floating Point Unit. If we only have floating point emulation, then there
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@ -102,6 +102,12 @@
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"normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4"
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(const_string "normal"))
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; Load scheduling, set from the cpu characteristic
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(define_attr "ldsched" "no,yes"
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(if_then_else (eq_attr "cpu" "arm8,st_arm")
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(const_string "yes")
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(const_string "no")))
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; condition codes: this one is used by final_prescan_insn to speed up
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; conditionalizing instructions. It saves having to scan the rtl to see if
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; it uses or alters the condition codes.
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@ -210,13 +216,23 @@
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(define_function_unit "write_blockage" 1 0
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(eq_attr "write_conflict" "yes") 1 1)
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(define_function_unit "core" 1 1 (eq_attr "core_cycles" "single") 1 1)
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(define_function_unit "core" 1 1 (eq_attr "type" "load") 2 2)
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(define_function_unit "core" 1 1
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(and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) 1 1)
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(define_function_unit "core" 1 1
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(and (eq_attr "ldsched" "!yes") (eq_attr "type" "load")) 2 2)
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(define_function_unit "core" 1 1 (eq_attr "type" "mult") 16 16)
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(define_function_unit "core" 1 1 (eq_attr "type" "store1") 2 2)
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(define_function_unit "core" 1 1
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(and (eq_attr "ldsched" "yes") (eq_attr "type" "store1")) 1 1)
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(define_function_unit "core" 1 1
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(and (eq_attr "ldsched" "!yes") (eq_attr "type" "store1")) 2 2)
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(define_function_unit "core" 1 1 (eq_attr "type" "store2") 3 3)
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@ -228,6 +244,9 @@
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(and (eq_attr "core_cycles" "multi")
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(eq_attr "type" "!mult,load,store2,store3,store4")) 32 32)
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(define_function_unit "loader" 1 0
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(and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) 2 1)
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;; Note: For DImode insns, there is normally no reason why operands should
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;; not be in the same register, what we don't want is for something being
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@ -2420,6 +2439,11 @@
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: preserve_subexpressions_p ()));
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DONE;
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}
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if (CONSTANT_P (operands[1]) && flag_pic)
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operands[1] = legitimize_pic_address (operands[1], SImode,
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((reload_in_progress
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|| reload_completed)
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? operands[0] : 0));
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")
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(define_insn "*movsi_insn"
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@ -2463,6 +2487,46 @@
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&& GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT))"
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"adr%?\\t%0, %a1")
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/* When generating pic, we need to load the symbol offset into a register.
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So that the optimizer does not confuse this with a normal symbol load
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we use an unspec. The offset will be loaded from a constant pool entry,
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since that is the only type of relocation we can use. */
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(define_insn "pic_load_addr"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(unspec:SI [(match_operand 1 "" "")] 3))]
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"flag_pic"
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"ldr%?\\t%0, %a1"
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[(set_attr "type" "load")])
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;; This variant is used for AOF assembly, since it needs to mention the
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;; pic register in the rtl.
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(define_expand "pic_load_addr_based"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(unspec:SI [(match_operand 1 "" "") (match_dup 2)] 3))]
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"flag_pic"
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"operands[2] = pic_offset_table_rtx;")
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(define_insn "*pic_load_addr_based_insn"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(unspec:SI [(match_operand 1 "" "")
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(match_operand 2 "s_register_operand" "r")] 3))]
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"flag_pic && operands[2] == pic_offset_table_rtx"
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"*
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#ifdef AOF_ASSEMBLER
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operands[1] = aof_pic_entry (operands[1]);
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#endif
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output_asm_insn (\"ldr%?\\t%0, %a1\", operands);
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return \"\";
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" [(set_attr "type" "load")])
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(define_insn "pic_add_dot_plus_eight"
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[(set (pc) (label_ref (match_operand 0 "" "")))
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(set (match_operand 1 "register_operand" "+r")
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(plus:SI (match_dup 1) (const (plus:SI (pc) (const_int 8)))))]
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"flag_pic"
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"add%?\\t%1, %|pc, %1")
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;; If copying one reg to another we can set the condition codes according to
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;; its value. Such a move is common after a return from subroutine and the
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;; result is being tested against zero.
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@ -5775,98 +5839,6 @@
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[(set_attr "type" "call")
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(set_attr "length" "8")])
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;; If calling a subroutine and then jumping back to somewhere else, but not
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;; too far away, then we can set the link register with the branch address
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;; and jump direct to the subroutine. On return from the subroutine
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;; execution continues at the branch; this avoids a prefetch stall.
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;; We use the length attribute (via short_branch ()) to establish whether or
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;; not this is possible, this is the same as the sparc does.
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(define_peephole
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[(parallel[(call (mem:SI (match_operand:SI 0 "" "X"))
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(match_operand:SI 1 "general_operand" "g"))
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(clobber (reg:SI 14))])
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(set (pc)
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(label_ref (match_operand 2 "" "")))]
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"0 && GET_CODE (operands[0]) == SYMBOL_REF
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&& short_branch (INSN_UID (insn), INSN_UID (operands[2]))
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&& arm_insn_not_targeted (insn)"
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"*
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{
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int backward = arm_backwards_branch (INSN_UID (insn),
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INSN_UID (operands[2]));
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#if 0
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/* Putting this in means that TARGET_6 code will ONLY run on an arm6 or
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* above, leaving it out means that the code will still run on an arm 2 or 3
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*/
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if (TARGET_6)
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{
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if (backward)
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output_asm_insn (\"sub%?\\t%|lr, %|pc, #(8 + . -%l2)\", operands);
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else
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output_asm_insn (\"add%?\\t%|lr, %|pc, #(%l2 - . -8)\", operands);
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}
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else
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#endif
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{
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output_asm_insn (\"mov%?\\t%|lr, %|pc\\t%@ protect cc\", operands);
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if (backward)
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output_asm_insn (\"sub%?\\t%|lr, %|lr, #(4 + . -%l2)\", operands);
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else
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output_asm_insn (\"add%?\\t%|lr, %|lr, #(%l2 - . -4)\", operands);
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}
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return \"b%?\\t%a0\";
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}"
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[(set_attr "type" "call")
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(set (attr "length")
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(if_then_else (eq_attr "prog_mode" "prog32")
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(const_int 8)
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(const_int 12)))])
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(define_peephole
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[(parallel[(set (match_operand:SI 0 "s_register_operand" "=r")
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(call (mem:SI (match_operand:SI 1 "" "X"))
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(match_operand:SI 2 "general_operand" "g")))
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(clobber (reg:SI 14))])
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(set (pc)
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(label_ref (match_operand 3 "" "")))]
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"0 && GET_CODE (operands[0]) == SYMBOL_REF
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&& short_branch (INSN_UID (insn), INSN_UID (operands[3]))
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&& arm_insn_not_targeted (insn)"
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"*
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{
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int backward = arm_backwards_branch (INSN_UID (insn),
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INSN_UID (operands[3]));
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#if 0
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/* Putting this in means that TARGET_6 code will ONLY run on an arm6 or
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* above, leaving it out means that the code will still run on an arm 2 or 3
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*/
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if (TARGET_6)
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{
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if (backward)
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output_asm_insn (\"sub%?\\t%|lr, %|pc, #(8 + . -%l3)\", operands);
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else
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output_asm_insn (\"add%?\\t%|lr, %|pc, #(%l3 - . -8)\", operands);
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}
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else
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#endif
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{
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output_asm_insn (\"mov%?\\t%|lr, %|pc\\t%@ protect cc\", operands);
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if (backward)
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output_asm_insn (\"sub%?\\t%|lr, %|lr, #(4 + . -%l3)\", operands);
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else
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output_asm_insn (\"add%?\\t%|lr, %|lr, #(%l3 - . -4)\", operands);
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}
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return \"b%?\\t%a1\";
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}"
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[(set_attr "type" "call")
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(set (attr "length")
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(if_then_else (eq_attr "prog_mode" "prog32")
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(const_int 8)
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(const_int 12)))])
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(define_split
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[(set (match_operand:SI 0 "s_register_operand" "")
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(and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "")
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