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testsuite: adjustments for amdgcn

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2020-03-25  Andrew Stubbs  <ams@codesourcery.com>

	gcc/testsuite/
	* gcc.dg/vect/bb-slp-pr69907.c: Disable the dump scan for amdgcn.
	* lib/target-supports.exp (check_effective_target_vect_unpack):
	Add amdgcn.
This commit is contained in:
Andrew Stubbs 2020-03-03 23:16:13 +00:00
parent 48817fbd76
commit fe4b53b2e7
3 changed files with 11 additions and 3 deletions
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6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2020-03-25 Andrew Stubbs <ams@codesourcery.com>
* gcc.dg/vect/bb-slp-pr69907.c: Disable the dump scan for amdgcn.
* lib/target-supports.exp (check_effective_target_vect_unpack):
Add amdgcn.
2020-03-25 Jakub Jelinek <jakub@redhat.com>
PR target/94292

5
gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
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@ -19,5 +19,6 @@ void foo(unsigned *p1, unsigned short *p2)
/* Disable for SVE because for long or variable-length vectors we don't
get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD,
because there we can vectorize the epilogue using mixed vector sizes. */
/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { ! aarch64*-*-* } } } } */
because there we can vectorize the epilogue using mixed vector sizes.
Likewise for AMD GCN. */
/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */

3
gcc/testsuite/lib/target-supports.exp
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@ -6717,7 +6717,8 @@ proc check_effective_target_vect_unpack { } {
|| ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
&& [check_effective_target_arm_little_endian])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn*-*-*] }}]
}
# Return 1 if the target plus current options does not guarantee