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config.gcc: Remove support for sparc-*-openbsd*...

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gcc/
	* config.gcc: Remove support for sparc-*-openbsd*,
	i860-*-sysv4*, ip2k-*-elf, ns32k-*-netbsdelf*,
	ns32k-*-netbsd*.
	* config.host: Remove support for i860-*-sysv4* as a host.
	* config/i860/*, config/ip2k/*, config/ns32k/*,
	config/sparc/openbsd.h, config/sparc/t-openbsd: Remove.
	* doc/install.texi, doc/invoke.texi, doc/md.texi: Don't
	mention obsolete ports.

testsuite/
	* gcc.dg/20020312-2.c, gcc.dg/sibcall-3.c, gcc.dg/sibcall-4.c,
	gcc.dg/cpp/assert4.c: Don't mention obsolete ports.

From-SVN: r102189
This commit is contained in:
Kazu Hirata 2005-07-20 06:39:38 +00:00 committed by Kazu Hirata
parent 96a2347e1d
commit fdda361d74
40 changed files with 19 additions and 28579 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
gcc/ChangeLog
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@ -1,3 +1,14 @@
2005-07-20 Kazu Hirata <kazu@codesourcery.com>
* config.gcc: Remove support for sparc-*-openbsd*,
i860-*-sysv4*, ip2k-*-elf, ns32k-*-netbsdelf*,
ns32k-*-netbsd*.
* config.host: Remove support for i860-*-sysv4* as a host.
* config/i860/*, config/ip2k/*, config/ns32k/*,
config/sparc/openbsd.h, config/sparc/t-openbsd: Remove.
* doc/install.texi, doc/invoke.texi, doc/md.texi: Don't
mention obsolete ports.
2005-07-20 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (regno_reg_class): Add GENERAL_REGS for

35
gcc/config.gcc
View File

@ -184,12 +184,7 @@ md_file=
# Obsolete configurations.
case ${target} in
sparc-*-openbsd* \
| i860-*-sysv4* \
| ip2k-*-elf \
| ns32k-*-netbsdelf* \
| ns32k-*-netbsd* \
| c4x-* \
c4x-* \
| tic4x-* \
)
if test "x$enable_obsolete" != xyes; then
@ -1226,12 +1221,6 @@ i[34567]86-*-kaos*)
tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h i386/i386elf.h kaos.h i386/kaos-i386.h"
tmake_file="i386/t-i386elf t-svr4"
;;
i860-*-sysv4*)
tm_file="${tm_file} elfos.h svr4.h i860/sysv4.h"
tmake_file="i860/t-i860 i860/t-svr4"
extra_parts="crtbegin.o crtend.o"
use_fixproto=yes
;;
ia64*-*-elf*)
tm_file="${tm_file} dbxelf.h elfos.h ia64/sysv4.h ia64/elf.h"
tmake_file="ia64/t-ia64"
@ -1279,10 +1268,6 @@ ia64*-*-hpux*)
# in ia64/t-hpux, and also fix the definition of putenv in
# sys-protos.h (const char not char).
;;
ip2k-*-elf)
tm_file="elfos.h ${tm_file}"
use_fixproto=yes
;;
iq2000*-*-elf*)
tm_file="svr4.h elfos.h iq2000/iq2000.h"
tmake_file=iq2000/t-iq2000
@ -1557,16 +1542,6 @@ mn10300-*-*)
use_collect2=no
use_fixproto=yes
;;
ns32k-*-netbsdelf*)
echo "GCC does not yet support the ${target} target"; exit 1
;;
ns32k-*-netbsd*)
tm_file="${tm_file} netbsd.h netbsd-aout.h ns32k/netbsd.h"
# On NetBSD, the headers are already okay, except for math.h.
tmake_file="t-netbsd ns32k/t-ns32k"
extra_parts=""
use_collect2=yes
;;
pdp11-*-bsd)
tm_file="${tm_file} pdp11/2bsd.h"
use_fixproto=yes
@ -1995,14 +1970,6 @@ sparc-*-netbsdelf*)
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h netbsd.h netbsd-elf.h sparc/netbsd-elf.h"
extra_options="${extra_options} sparc/long-double-switch.opt"
;;
sparc-*-openbsd*)
tm_defines=OBSD_OLD_GAS
tm_file="sparc/sparc.h openbsd.h sparc/openbsd.h"
# needed to unconfuse gdb
tmake_file="t-libc-ok t-openbsd sparc/t-openbsd"
# we need collect2 until our bug is fixed...
use_collect2=yes
;;
sparc64-*-openbsd*)
tm_file="sparc/openbsd1-64.h ${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sp64-elf.h openbsd.h sparc/openbsd64.h"
extra_options="${extra_options} sparc/little-endian.opt"

3
gcc/config.host
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@ -177,9 +177,6 @@ case ${host} in
out_host_hook_obj="${out_host_hook_obj} host-i386-darwin.o"
host_xmake_file="${host_xmake_file} i386/x-darwin"
;;
i860-*-sysv4*)
host_xmake_file=i860/x-sysv4
;;
powerpc-*-beos*)
host_can_use_collect2=no
;;

53
gcc/config/i860/i860-protos.h
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@ -1,53 +0,0 @@
/* Definitions of target machine for GNU compiler, for Intel 860.
Copyright (C) 2000, 2003, 2004 Free Software Foundation, Inc.
Hacked substantially by Ron Guilmette (rfg@monkeys.com) to cater to
the whims of the System V Release 4 assembler.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
/* Declare things which are defined in i860.c but called from
insn-output.c. */
#ifdef RTX_CODE
extern unsigned long sfmode_constant_to_ulong (rtx);
extern const char *output_load (rtx *);
extern const char *output_store (rtx *);
extern const char *output_move_double (rtx *);
extern const char *output_fp_move_double (rtx *);
extern const char *output_block_move (rtx *);
extern void output_load_address (rtx *);
extern int safe_insn_src_p (rtx, enum machine_mode);
extern int operand_clobbered_before_used_after (rtx, rtx);
extern int reg_or_0_operand (rtx, enum machine_mode);
extern int arith_operand (rtx, enum machine_mode);
extern int logic_operand (rtx, enum machine_mode);
extern int shift_operand (rtx, enum machine_mode);
extern int compare_operand (rtx, enum machine_mode);
extern int bte_operand (rtx, enum machine_mode);
extern int indexed_operand (rtx, enum machine_mode);
extern int load_operand (rtx, enum machine_mode);
extern int small_int (rtx, enum machine_mode);
extern int logic_int (rtx, enum machine_mode);
extern int call_insn_operand (rtx, enum machine_mode);
#ifdef TREE_CODE
extern void i860_va_start (tree, rtx);
#endif /* TREE_CODE */
#endif /* RTX_CODE */
extern void tdesc_section (void);

2127
gcc/config/i860/i860.c
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1217
gcc/config/i860/i860.h
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2231
gcc/config/i860/i860.md
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32
gcc/config/i860/i860.opt
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@ -1,32 +0,0 @@
; Options for the Intel i860 port of the compiler.
; Copyright (C) 2005 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 2, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING. If not, write to the Free
; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
; 02110-1301, USA.
mxp
Target Report RejectNegative Mask(XP)
Generate code which uses the FPU
mnoxp
Target Report RejectNegative InverseMask(XP)
Do not generate code which uses the FPU
mxr
Target Report RejectNegative InverseMask(XP)
Do not generate code which uses the FPU

155
gcc/config/i860/sysv4.h
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@ -1,155 +0,0 @@
/* Target definitions for GNU compiler for Intel 80860 running System V.4
Copyright (C) 1991, 1996, 2000, 2002, 2003 Free Software Foundation, Inc.
Contributed by Ron Guilmette (rfg@monkeys.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (i860 System V Release 4)");
#undef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX ""
/* Provide a set of pre-definitions and pre-assertions appropriate for
the i860 running svr4. Note that the symbol `__svr4__' MUST BE
DEFINED! It is needed so that the va_list struct in va-i860.h
will get correctly defined for the svr4 (ABI compliant) case rather
than for the previous (svr3, svr2, ...) case. It also needs to be
defined so that the correct (svr4) version of __builtin_saveregs
will be selected when we are building gnulib2.c.
__svr4__ is our extension. */
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("unix"); \
builtin_define ("SVR4"); \
builtin_define ("__svr4__"); \
builtin_assert ("system=unix"); \
builtin_assert ("system=svr4"); \
} \
while (0)
/* For the benefit of i860_va_arg, flag it this way too. */
#define I860_SVR4_VA_LIST 1
/* The prefix to be used in assembler output for all names of registers.
This string gets prepended to all i860 register names (svr4 only). */
#define I860_REG_PREFIX "%"
#define ASM_COMMENT_START "#"
#undef TYPE_OPERAND_FMT
#define TYPE_OPERAND_FMT "\"%s\""
#define GLOBAL_ASM_OP ".globl "
/* The following macro definition overrides the one in i860.h
because the svr4 i860 assembler requires a different syntax
for getting parts of constant/relocatable values. */
#undef PRINT_OPERAND_PART
#define PRINT_OPERAND_PART(FILE, X, PART_CODE) \
do { fprintf (FILE, "["); \
output_address (X); \
fprintf (FILE, "]@%s", PART_CODE); \
} while (0)
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START i860_file_start
/* Output the special word the svr4 SDB wants to see just before
the first word of each function's prologue code. */
extern const char *current_function_original_name;
/* This special macro is used to output a magic word just before the
first word of each function. On some versions of UNIX running on
the i860, this word can be any word that looks like a NOP, however
under svr4, this neds to be an `shr r0,r0,r0' instruction in which
the normally unused low-order bits contain the length of the function
prologue code (in bytes). This is needed to make the svr4 SDB debugger
happy. */
#undef ASM_OUTPUT_FUNCTION_PREFIX
#define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \
do { ASM_OUTPUT_ALIGN (FILE, 2); \
fprintf ((FILE), "\t.long\t.ep."); \
assemble_name (FILE, FNNAME); \
fprintf (FILE, "-"); \
assemble_name (FILE, FNNAME); \
fprintf (FILE, "+0xc8000000\n"); \
current_function_original_name = (FNNAME); \
} while (0)
/* Output the special label that must go just after each function's
prologue code to support svr4 SDB. */
#define ASM_OUTPUT_PROLOGUE_SUFFIX(FILE) \
do { fprintf (FILE, ".ep."); \
assemble_name (FILE, current_function_original_name); \
fprintf (FILE, ":\n"); \
} while (0)
/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
Note that we want to give these sections the SHF_WRITE attribute
because these sections will actually contain data (i.e. tables of
addresses of functions in the current root executable or shared library
file) and, in the case of a shared library, the relocatable addresses
will have to be properly resolved/relocated (and then written into) by
the dynamic linker when it actually attaches the given shared library
to the executing process. (Note that on SVR4, you may wish to use the
`-z text' option to the ELF linker, when building a shared library, as
an additional check that you are doing everything right. But if you do
use the `-z text' option when building a shared library, you will get
errors unless the .ctors and .dtors sections are marked as writable
via the SHF_WRITE attribute.) */
#undef CTORS_SECTION_ASM_OP
#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
#undef DTORS_SECTION_ASM_OP
#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
/* Add definitions to support the .tdesc section as specified in the svr4
ABI for the i860. */
#define TDESC_SECTION_ASM_OP "\t.section\t.tdesc"
#undef EXTRA_SECTIONS
#define EXTRA_SECTIONS in_tdesc
#undef EXTRA_SECTION_FUNCTIONS
#define EXTRA_SECTION_FUNCTIONS \
TDESC_SECTION_FUNCTION
#define TDESC_SECTION_FUNCTION \
void \
tdesc_section () \
{ \
if (in_section != in_tdesc) \
{ \
fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP); \
in_section = in_tdesc; \
} \
}

5
gcc/config/i860/t-i860
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@ -1,5 +0,0 @@
LIB2FUNCS_EXTRA = varargs.asm
varargs.asm: $(srcdir)/config/i860/varargs.asm
cp $(srcdir)/config/i860/varargs.asm .

212
gcc/config/i860/varargs.asm
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@ -1,212 +0,0 @@
/* Special varargs support for i860.
Copyright (C) 2001, 2003 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
In addition to the permissions in the GNU General Public License, the
Free Software Foundation gives you unlimited permission to link the
compiled version of this file into combinations with other programs,
and to distribute those combinations without any restriction coming
from the use of this file. (The General Public License restrictions
do apply in other respects; for example, they cover modification of
the file, and distribution when not linked into a combine
executable.)
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
#if defined(__svr4__) || defined(__alliant__)
.text
.align 4
/* The Alliant needs the added underscore. */
.globl __builtin_saveregs
__builtin_saveregs:
.globl ___builtin_saveregs
___builtin_saveregs:
andnot 0x0f,%sp,%sp /* round down to 16-byte boundary */
#if 0
adds -96,%sp,%sp /* allocate stack space for reg save
area and also for a new va_list
structure */
#else
adds -80,%sp,%sp /* allocate stack space for reg save area */
#endif
/* Save all argument registers in the arg reg save area. The
arg reg save area must have the following layout (according
to the svr4 ABI):
struct {
union {
float freg[8];
double dreg[4];
} float_regs;
long ireg[12];
};
*/
fst.q %f8, 0(%sp) /* save floating regs (f8-f15) */
fst.q %f12,16(%sp)
st.l %r16,32(%sp) /* save integer regs (r16-r27) */
st.l %r17,36(%sp)
st.l %r18,40(%sp)
st.l %r19,44(%sp)
st.l %r20,48(%sp)
st.l %r21,52(%sp)
st.l %r22,56(%sp)
st.l %r23,60(%sp)
st.l %r24,64(%sp)
st.l %r25,68(%sp)
st.l %r26,72(%sp)
st.l %r27,76(%sp)
#if 0
adds 80,%sp,%r16 /* compute the address of the new
va_list structure. Put in into
r16 so that it will be returned
to the caller. */
#endif
/* Initialize all fields of the new va_list structure. This
structure looks like:
typedef struct {
unsigned long ireg_used;
unsigned long freg_used;
long *reg_base;
long *mem_ptr;
} va_list;
*/
#if 0
st.l %r0, 0(%r16) /* nfixed */
st.l %r0, 4(%r16) /* nfloating */
st.l %sp, 8(%r16) /* __va_ctl points to __va_struct. */
bri %r1 /* delayed return */
st.l %r28,12(%r16) /* pointer to overflow args */
#else
bri %r1 /* delayed return */
or %sp,%r0,%r16 /* Return the address of the reg save area. */
#endif
#else /* not __svr4__ */
#if defined(__PARAGON__)
/*
* we'll use SVR4-ish varargs but need SVR3.2 assembler syntax,
* and we stand a better chance of hooking into libraries
* compiled by PGI. [andyp@ssd.intel.com]
*/
.text
.align 4
.globl __builtin_saveregs
__builtin_saveregs:
.globl ___builtin_saveregs
___builtin_saveregs:
andnot 0x0f,sp,sp /* round down to 16-byte boundary */
adds -96,sp,sp /* allocate stack space for reg save
area and also for a new va_list
structure */
/* Save all argument registers in the arg reg save area. The
arg reg save area must have the following layout (according
to the svr4 ABI):
struct {
union {
float freg[8];
double dreg[4];
} float_regs;
long ireg[12];
};
*/
fst.q f8, 0(sp)
fst.q f12,16(sp)
st.l r16,32(sp)
st.l r17,36(sp)
st.l r18,40(sp)
st.l r19,44(sp)
st.l r20,48(sp)
st.l r21,52(sp)
st.l r22,56(sp)
st.l r23,60(sp)
st.l r24,64(sp)
st.l r25,68(sp)
st.l r26,72(sp)
st.l r27,76(sp)
adds 80,sp,r16 /* compute the address of the new
va_list structure. Put in into
r16 so that it will be returned
to the caller. */
/* Initialize all fields of the new va_list structure. This
structure looks like:
typedef struct {
unsigned long ireg_used;
unsigned long freg_used;
long *reg_base;
long *mem_ptr;
} va_list;
*/
st.l r0, 0(r16) /* nfixed */
st.l r0, 4(r16) /* nfloating */
st.l sp, 8(r16) /* __va_ctl points to __va_struct. */
bri r1 /* delayed return */
st.l r28,12(r16) /* pointer to overflow args */
#else /* not __PARAGON__ */
.text
.align 4
.globl ___builtin_saveregs
___builtin_saveregs:
mov sp,r30
andnot 0x0f,sp,sp
adds -96,sp,sp /* allocate sufficient space on the stack */
/* Fill in the __va_struct. */
st.l r16, 0(sp) /* save integer regs (r16-r27) */
st.l r17, 4(sp) /* int fixed[12] */
st.l r18, 8(sp)
st.l r19,12(sp)
st.l r20,16(sp)
st.l r21,20(sp)
st.l r22,24(sp)
st.l r23,28(sp)
st.l r24,32(sp)
st.l r25,36(sp)
st.l r26,40(sp)
st.l r27,44(sp)
fst.q f8, 48(sp) /* save floating regs (f8-f15) */
fst.q f12,64(sp) /* int floating[8] */
/* Fill in the __va_ctl. */
st.l sp, 80(sp) /* __va_ctl points to __va_struct. */
st.l r28,84(sp) /* pointer to more args */
st.l r0, 88(sp) /* nfixed */
st.l r0, 92(sp) /* nfloating */
adds 80,sp,r16 /* return address of the __va_ctl. */
bri r1
mov r30,sp
/* recover stack and pass address to start
of data. */
#endif /* not __PARAGON__ */
#endif /* not __svr4__ */

44
gcc/config/i860/x-sysv4
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@ -1,44 +0,0 @@
# The svr4 reference port for the i860 contains an alloca.o routine
# in /usr/ucblib/libucb.a, but we can't just try to get that by
# setting CLIB to /usr/ucblib/libucb.a because (unfortunately)
# there are a lot of other routines in libucb.a which are supposed
# to be the Berkeley versions of library routines normally found in
# libc.a and many of these Berkeley versions are badly broken. Thus,
# if we try to link programs with libucb.a before libc.a, those
# programs tend to crash.
# Also, the alloca() routine supplied in early version of svr4 for
# the i860 is non-ABI compliant. It doesn't keep the stack aligned
# to a 16-byte boundary as the ABI requires.
# More importantly however, even a fully ABI compliant alloca() routine
# would fail to work correctly with some versions of the native svr4 C
# compiler currently being distributed for the i860 (as of 1/29/92).
# The problem is that the native C compiler generates non-ABI-compliant
# function epilogues which cut back the stack (upon function exit) in
# an incorrect manner. Specifically, they cut back the stack by adding
# the nominal *static* frame size (determined statically at compile-time)
# to the stack pointer rather than setting the stack pointer based upon
# the current value of the frame pointer (as called for in the i860 ABI).
# This can cause serious trouble in cases where you repeatedly call a
# routine which itself calls alloca(). In such cases, the stack will
# grow continuously until you finally run out of swap space or exceed
# the system's process size limit. To avoid this problem (which can
# arise when a stage1 gcc is being used to build a stage2 gcc) you
# *must* link in the C language version of alloca() which is supplied
# with gcc to your stage1 version of gcc. The following definition
# forces that to happen.
ALLOCA=alloca.o
# We build all stages *without* shared libraries because that may make
# debugging the compiler easier (until there is a GDB which supports
# both Dwarf *and* svr4 shared libraries).
# Note that the native C compiler for the svr4 reference port on the
# i860 recognizes a special -gg option. Using that option causes *full*
# Dwarf debugging information to be generated, whereas using only -g
# causes only limited Dwarf debugging information to be generated.
# (This is an undocumented feature of the native svr4 C compiler.)
CCLIBFLAGS=-Bstatic -dn -gg

53
gcc/config/ip2k/crt0.S
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@ -1,53 +0,0 @@
;
; Copyright (C) 2000, 2001 Free Software Foundation, Inc.
; Contributed by Red Hat, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2, or (at your option)
; any later version.
;
; In addition to the permissions in the GNU General Public License, the
; Free Software Foundation gives you unlimited permission to link the
; compiled version of this file with other programs, and to distribute
; those programs without any restriction coming from the use of this
; file. (The General Public License restrictions do apply in other
; respects; for example, they cover modification of the file, and
; distribution when not linked into another program.)
;
; GCC is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING. If not, write to
; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
; Boston, MA 02110-1301, USA.
;
.file "crt0.S"
.text
.global __start
.func __start
__start:
clr $ff ; Insure we have a zero available
mov w,#%hi8data(__stack) ; set up stack
mov sph,w ;
mov w,#%lo8data(__stack)
mov spl,w
push #0 ; Set argc/argv.
push #0 ; Only required for testing
push #0 ; purposes and "ansi" main.
push #0
page _main
call _main
push $81 ; use return value to call exit()
push $80
page _exit
call _exit
break ; Should never return
.endfunc

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gcc/config/ip2k/ip2k-protos.h
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@ -1,83 +0,0 @@
/* Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
Contributed by Red Hat, Inc and Ubicom, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
extern void function_prologue (FILE *, HOST_WIDE_INT);
extern void function_epilogue (FILE *, HOST_WIDE_INT);
extern int find_one_set_bit_p (HOST_WIDE_INT);
extern int find_one_clear_bit_p (HOST_WIDE_INT);
#ifdef TREE_CODE
extern void unique_section (tree, int);
extern int valid_machine_type_attribute (tree, tree, tree, tree);
extern int valid_machine_decl_attribute (tree, tree, tree, tree);
extern int ip2k_return_pops_args (tree, tree, int);
#endif /* TREE_CODE */
#ifdef RTX_CODE
extern int legitimate_address_p (enum machine_mode, rtx, int);
extern int ip2k_extra_constraint (rtx, int);
extern rtx legitimize_address (rtx, rtx, enum machine_mode, rtx);
extern int adjust_insn_length (rtx insn, int len);
extern void asm_output_char (FILE *, rtx);
extern void asm_output_short (FILE *, rtx);
extern void asm_output_byte (FILE *, int);
extern void print_operand (FILE *, rtx, int);
extern void print_operand_address (FILE *, rtx);
extern int ip2k_jump_mode (rtx, rtx);
extern void ip2k_split_words (enum machine_mode, enum machine_mode, rtx *);
extern rtx ip2k_get_low_half (rtx, enum machine_mode);
extern rtx ip2k_get_high_half (rtx, enum machine_mode);
extern int ip2k_nonptr_operand (rtx, enum machine_mode);
extern int ip2k_ptr_operand (rtx, enum machine_mode);
extern int ip2k_ip_operand (rtx, enum machine_mode);
extern int ip2k_short_operand (rtx, enum machine_mode);
extern int ip2k_gen_operand (rtx, enum machine_mode);
extern int ip2k_nonsp_reg_operand (rtx, enum machine_mode);
extern int ip2k_symbol_ref_operand (rtx, enum machine_mode);
extern const char *ip2k_set_compare (rtx, rtx);
extern const char *ip2k_gen_sCOND (rtx, enum rtx_code, rtx);
extern const char *ip2k_gen_signed_comp_branch (rtx, enum rtx_code, rtx);
extern const char *ip2k_gen_unsigned_comp_branch (rtx, enum rtx_code, rtx);
extern int is_regfile_address (rtx);
extern int ip2k_mode_dependent_address (rtx);
extern int ip2k_address_uses_reg_p (rtx, unsigned int);
extern int ip2k_xexp_not_uses_reg_p (rtx, unsigned int, int);
extern int ip2k_composite_xexp_not_uses_reg_p (rtx, unsigned int, int);
extern int ip2k_composite_xexp_not_uses_cc0_p (rtx);
extern int ip2k_signed_comparison_operator (rtx, enum machine_mode);
extern int ip2k_unsigned_comparison_operator (rtx, enum machine_mode);
extern int ip2k_unary_operator (rtx, enum machine_mode);
extern int ip2k_binary_operator (rtx, enum machine_mode);
extern rtx ip2k_compare_operands[3];
#endif /* RTX_CODE */
#ifdef HAVE_MACHINE_MODES
extern int class_max_nregs (enum reg_class, enum machine_mode);
extern enum reg_class class_likely_spilled_p (int c);
#endif /* HAVE_MACHINE_MODES */
#ifdef REAL_VALUE_TYPE
extern void asm_output_float (FILE *, REAL_VALUE_TYPE);
#endif
extern int ip2k_init_elim_offset (int, int);
extern void ip2k_init_local_alloc (int *);

6217
gcc/config/ip2k/ip2k.c
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851
gcc/config/ip2k/ip2k.h
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@ -1,851 +0,0 @@
/* Definitions of target machine for GCC,
For Ubicom IP2022 Communications Controller
Copyright (C) 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by Red Hat, Inc and Ubicom, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
#undef ASM_SPEC /* We have a GAS assembler. */
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("IP2K"); \
builtin_define ("_DOUBLE_IS_32BITS"); \
builtin_define ("_BUFSIZ=512"); \
builtin_define ("__FILENAME_MAX__=128"); \
} \
while (0)
#define TARGET_VERSION fprintf (stderr, " (ip2k, GNU assembler syntax)")
/* Caller-saves is not a win for the IP2K. Pretty much anywhere that
a register is permitted allows SP-relative addresses too.
This machine doesn't have PIC addressing modes, so disable that also. */
#define OVERRIDE_OPTIONS \
do { \
flag_caller_saves = 0; \
flag_pic = 0; \
} while (0)
/* Put each function in its own section so that PAGE-instruction
relaxation can do its best. */
#define OPTIMIZATION_OPTIONS(LEVEL, SIZEFLAG) \
do { \
if ((LEVEL) || (SIZEFLAG)) \
flag_function_sections = 1; \
} while (0)
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN 1
#define WORDS_BIG_ENDIAN 1
#define BITS_PER_WORD 8
#define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
#define POINTER_SIZE 16
/* Maximum sized of reasonable data type DImode or Dfmode ... */
#define MAX_FIXED_MODE_SIZE 64
#define PARM_BOUNDARY 8
#define FUNCTION_BOUNDARY 16
#define EMPTY_FIELD_BOUNDARY 8
#define BIGGEST_ALIGNMENT 8
#define STRICT_ALIGNMENT 0
#define PCC_BITFIELD_TYPE_MATTERS 1
#undef INT_TYPE_SIZE
#define INT_TYPE_SIZE 16
#undef SHORT_TYPE_SIZE
#define SHORT_TYPE_SIZE 16
#undef LONG_TYPE_SIZE
#define LONG_TYPE_SIZE 32
#undef LONG_LONG_TYPE_SIZE
#define LONG_LONG_TYPE_SIZE 64
#undef CHAR_TYPE_SIZE
#define CHAR_TYPE_SIZE 8
#undef FLOAT_TYPE_SIZE
#define FLOAT_TYPE_SIZE 32
#undef DOUBLE_TYPE_SIZE
#define DOUBLE_TYPE_SIZE 32
#undef LONG_DOUBLE_TYPE_SIZE
#define LONG_DOUBLE_TYPE_SIZE 32
#define DEFAULT_SIGNED_CHAR 1
#define SIZE_TYPE "unsigned int"
#define PTRDIFF_TYPE "int"
#undef WCHAR_TYPE
#define WCHAR_TYPE "int"
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 16
#define HARD_REG_SIZE (UNITS_PER_WORD)
/* Standard register usage.
for the IP2K, we are going to have a LOT of registers, but only some of them
are named. */
#define FIRST_PSEUDO_REGISTER (0x104) /* Skip over physical regs, VFP, AP. */
#define REG_IP 0x4
#define REG_IPH REG_IP
#define REG_IPL 0x5
#define REG_SP 0x6
#define REG_SPH REG_SP
#define REG_SPL 0x7
#define REG_PCH 0x8
#define REG_PCL 0x9
#define REG_W 0xa
#define REG_STATUS 0xb
#define REG_DP 0xc
#define REG_DPH REG_DP
#define REG_DPL 0xd
#define REG_MULH 0xf
#define REG_CALLH 0x7e /* Call-stack readout. */
#define REG_CALLL 0x7f
#define REG_RESULT 0x80 /* Result register (upto 8 bytes). */
#define REG_FP 0xfd /* 2 bytes for FRAME chain */
#define REG_ZERO 0xff /* Initialized to zero by runtime. */
#define REG_VFP 0x100 /* Virtual frame pointer. */
#define REG_AP 0x102 /* Virtual arg pointer. */
/* Status register bits. */
#define Z_FLAG 0x2
#define DC_FLAG 0x1
#define C_FLAG 0x0
#define FIXED_REGISTERS {\
1,1,1,1,0,0,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r0.. r31*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r32.. r63*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r64.. r95*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r96..r127*/\
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,/*r128..r159*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r160..r191*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r192..r223*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r224..r255*/\
1,1,1,1}
#define CALL_USED_REGISTERS { \
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r0.. r31*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r32.. r63*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r64.. r95*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r96..r127*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r128..r159*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r160..r191*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r192..r223*/\
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r224..r255*/\
1,1,1,1}
#define REG_ALLOC_ORDER { \
0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f, \
0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97, \
0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f, \
0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7, \
0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf, \
0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, \
0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf, \
0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7, \
0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf, \
0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7, \
0xd8,0xd9,0xda,0xdb,0xdc,0xdd,0xde,0xdf, \
0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, \
0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef, \
0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, \
0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff, \
0x00,0x01,0x02,0x03,0x0c,0x0d,0x06,0x07, \
0x08,0x09,0x0a,0x0b,0x04,0x05,0x0e,0x0f, \
0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, \
0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f, \
0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, \
0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, \
0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, \
0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, \
0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47, \
0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f, \
0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57, \
0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f, \
0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, \
0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f, \
0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77, \
0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f, \
0x100,0x101,0x102,0x103}
#define ORDER_REGS_FOR_LOCAL_ALLOC ip2k_init_local_alloc (reg_alloc_order)
/* Are we allowed to rename registers? For some reason, regrename was
changing DP to IP (when it appeared in addresses like (plus:HI
(reg: DP) (const_int 37)) - and that's bad because IP doesn't
permit offsets! */
#define HARD_REGNO_RENAME_OK(REG, NREG) \
(((REG) == REG_DPH) ? 0 \
: ((REG) == REG_IPH) ? ((NREG) == REG_DPH) \
: (((NREG) == REG_IPL) || ((NREG) == REG_DPL)) ? 0 : 1)
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
#define MODES_TIEABLE_P(MODE1, MODE2) \
(((MODE1) == QImode && (MODE2) == HImode) \
|| ((MODE2) == QImode && (MODE1) == HImode))
/* We originally had this as follows - this isn't a win on the IP2k
though as registers just get in our way!
#define MODES_TIEABLE_P(MODE1, MODE2) \
(((MODE1) > HImode && (MODE2) == HImode)
|| ((MODE1) == HImode && (MODE2) > HImode)) */
enum reg_class {
NO_REGS,
DPH_REGS,
DPL_REGS,
DP_REGS,
SP_REGS,
IPH_REGS,
IPL_REGS,
IP_REGS,
DP_SP_REGS,
PTR_REGS,
NONPTR_REGS,
NONSP_REGS,
GENERAL_REGS,
ALL_REGS = GENERAL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int)LIM_REG_CLASSES
#define REG_CLASS_NAMES { \
"NO_REGS", \
"DPH_REGS", \
"DPL_REGS", \
"DP_REGS", \
"SP_REGS", \
"IPH_REGS", \
"IPL_REGS", \
"IP_REGS", \
"DP_SP_REGS", \
"PTR_REGS", \
"NONPTR_REGS", \
"NONSP_REGS", \
"GENERAL_REGS" \
}
#define REG_CLASS_CONTENTS { \
{0x00000000, 0, 0, 0, 0, 0, 0, 0, 0}, /* NO_REGS */ \
{0x00001000, 0, 0, 0, 0, 0, 0, 0, 0}, /* DPH_REGS */ \
{0x00002000, 0, 0, 0, 0, 0, 0, 0, 0}, /* DPL_REGS */ \
{0x00003000, 0, 0, 0, 0, 0, 0, 0, 0}, /* DP_REGS */ \
{0x000000c0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SP_REGS */ \
{0x00000010, 0, 0, 0, 0, 0, 0, 0, 0}, /* IPH_REGS */ \
{0x00000020, 0, 0, 0, 0, 0, 0, 0, 0}, /* IPL_REGS */ \
{0x00000030, 0, 0, 0, 0, 0, 0, 0, 0}, /* IP_REGS */ \
{0x000030c0, 0, 0, 0, 0, 0, 0, 0, 0}, /* DP_SP_REGS */ \
{0x000030f0, 0, 0, 0, 0, 0, 0, 0, 0}, /* PTR_REGS */ \
{0xffffcf0f,-1,-1,-1,-1,-1,-1,-1, 0}, /* NONPTR_REGS */ \
{0xffffff3f,-1,-1,-1,-1,-1,-1,-1, 0}, /* NONSP_REGS */ \
{0xffffffff,-1,-1,-1,-1,-1,-1,-1,15} /* GENERAL_REGS */ \
}
#define REGNO_REG_CLASS(R) \
( (R) == REG_IPH ? IPH_REGS \
: (R) == REG_IPL ? IPL_REGS \
: (R) == REG_DPH ? DPH_REGS \
: (R) == REG_DPL ? DPL_REGS \
: (R) == REG_SPH ? SP_REGS \
: (R) == REG_SPL ? SP_REGS \
: NONPTR_REGS)
#define MODE_BASE_REG_CLASS(MODE) ((MODE) == QImode ? PTR_REGS : DP_SP_REGS)
#define BASE_REG_CLASS PTR_REGS
#define INDEX_REG_CLASS NO_REGS
#define REG_CLASS_FROM_LETTER(C) \
( (C) == 'j' ? IPH_REGS \
: (C) == 'k' ? IPL_REGS \
: (C) == 'f' ? IP_REGS \
: (C) == 'y' ? DPH_REGS \
: (C) == 'z' ? DPL_REGS \
: (C) == 'b' ? DP_REGS \
: (C) == 'u' ? NONSP_REGS \
: (C) == 'q' ? SP_REGS \
: (C) == 'c' ? DP_SP_REGS \
: (C) == 'a' ? PTR_REGS \
: (C) == 'd' ? NONPTR_REGS \
: NO_REGS)
#define REGNO_OK_FOR_BASE_P(R) \
((R) == REG_DP || (R) == REG_IP || (R) == REG_SP)
#define REGNO_MODE_OK_FOR_BASE_P(R,M) \
((R) == REG_DP || (R) == REG_SP \
|| ((R) == REG_IP && GET_MODE_SIZE (M) <= 1))
#define REGNO_OK_FOR_INDEX_P(NUM) 0
#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
#define SMALL_REGISTER_CLASSES 1
#define CLASS_LIKELY_SPILLED_P(CLASS) class_likely_spilled_p(CLASS)
#define CLASS_MAX_NREGS(CLASS, MODE) GET_MODE_SIZE (MODE)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? (VALUE) >= -255 && (VALUE) <= -1 : \
(C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 7 : \
(C) == 'K' ? (VALUE) >= 0 && (VALUE) <= 127 : \
(C) == 'L' ? (VALUE) > 0 && (VALUE) < 128: \
(C) == 'M' ? (VALUE) == -1: \
(C) == 'N' ? (VALUE) == 1: \
(C) == 'O' ? (VALUE) == 0: \
(C) == 'P' ? (VALUE) >= 0 && (VALUE) <= 255: \
0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
#define EXTRA_CONSTRAINT(X, C) ip2k_extra_constraint (X, C)
/* This is an undocumented variable which describes
how GCC will pop a data. */
#define STACK_POP_CODE PRE_INC
#define STACK_PUSH_CODE POST_DEC
#define STACK_CHECK_BUILTIN 1
/* Prologue code will do stack checking as necessary. */
#define STARTING_FRAME_OFFSET (0)
#define FRAME_GROWS_DOWNWARD 1
#define STACK_GROWS_DOWNWARD 1
/* On IP2K arg pointer is virtual and resolves to either SP or FP
after we've resolved what registers are saved (fp chain, return
pc, etc. */
#define FIRST_PARM_OFFSET(FUNDECL) 0
#define STACK_POINTER_OFFSET 1
/* IP2K stack is post-decremented, so 0(sp) is address of open space
and 1(sp) is offset to the location avobe the forst location at which
outgoing arguments are placed. */
#define STACK_BOUNDARY 8
#define STACK_POINTER_REGNUM REG_SP
#define FRAME_POINTER_REGNUM REG_VFP
#define HARD_FRAME_POINTER_REGNUM REG_FP
#define ARG_POINTER_REGNUM REG_AP
/* We don't really want to support nested functions. But we'll crash
in various testsuite tests if we don't at least define the register
to contain the static chain. The return value register is about as
bad a place as any for this. */
#define STATIC_CHAIN_REGNUM REG_RESULT
#define FRAME_POINTER_REQUIRED (!flag_omit_frame_pointer)
#define ELIMINABLE_REGS { \
{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
}
#define CAN_ELIMINATE(FROM, TO) \
((FROM) == HARD_FRAME_POINTER_REGNUM \
? (flag_omit_frame_pointer && !frame_pointer_needed) : 1)
/* Don't eliminate FP unless we EXPLICITLY_ASKED */
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
((OFFSET) = ip2k_init_elim_offset ((FROM), (TO)))
#define RETURN_ADDR_RTX(COUNT, X) \
(((COUNT) == 0) ? gen_rtx_REG (HImode, REG_CALLH) : NULL_RTX)
#define PUSH_ROUNDING(NPUSHED) (NPUSHED)
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
ip2k_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
#define CUMULATIVE_ARGS int
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
((CUM) = 0)
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)
/* All arguments are passed on stack - do nothing here. */
#define FUNCTION_ARG_REGNO_P(R) 0
#define FUNCTION_VALUE(VALTYPE, FUNC) \
((TYPE_MODE (VALTYPE) == QImode) \
? gen_rtx_REG (TYPE_MODE (VALTYPE), REG_RESULT + 1) \
: gen_rtx_REG (TYPE_MODE (VALTYPE), REG_RESULT))
/* Because functions returning 'char' actually widen to 'int', we have to
use $81 as the return location if we think we only have a 'char'. */
#define LIBCALL_VALUE(MODE) gen_rtx_REG ((MODE), REG_RESULT)
#define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_RESULT)
#define DEFAULT_PCC_STRUCT_RETURN 0
#define EPILOGUE_USES(REGNO) 0
/* Hmmm. We don't actually like constants as addresses - they always need
to be loaded to a register, except for function calls which take an
address by immediate value. But changing this to zero had negative
effects, causing the compiler to get very confused.... */
#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
#define MAX_REGS_PER_ADDRESS 1
#ifdef REG_OK_STRICT
# define GO_IF_LEGITIMATE_ADDRESS(MODE, OPERAND, ADDR) \
{ \
if (legitimate_address_p ((MODE), (OPERAND), 1)) \
goto ADDR; \
}
#else
# define GO_IF_LEGITIMATE_ADDRESS(MODE, OPERAND, ADDR) \
{ \
if (legitimate_address_p ((MODE), (OPERAND), 0)) \
goto ADDR; \
}
#endif
#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#define REG_OK_FOR_BASE_NOSTRICT_P(X) \
(REGNO (X) >= FIRST_PSEUDO_REGISTER \
|| (REGNO (X) == REG_FP) \
|| (REGNO (X) == REG_VFP) \
|| (REGNO (X) == REG_AP) \
|| REG_OK_FOR_BASE_STRICT_P(X))
#ifdef REG_OK_STRICT
# define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
#else
# define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NOSTRICT_P (X)
#endif
#define REG_OK_FOR_INDEX_P(X) 0
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
do { rtx orig_x = (X); \
(X) = legitimize_address ((X), (OLDX), (MODE), 0); \
if ((X) != orig_x && memory_address_p ((MODE), (X))) \
goto WIN; \
} while (0)
/* Is X a legitimate register to reload, or is it a pseudo stack-temp
that is problematic for push_reload() ? */
#define LRA_REG(X) \
(! (reg_equiv_memory_loc[REGNO (X)] \
&& (reg_equiv_address[REGNO (X)] \
|| num_not_at_initial_offset)))
/* Given a register X that failed the LRA_REG test, replace X
by its memory equivalent, find the reloads needed for THAT memory
location and substitute that back for the higher-level reload
that we're conducting... */
/* WARNING: we reference 'ind_levels' and 'insn' which are local variables
in find_reloads_address (), where the LEGITIMIZE_RELOAD_ADDRESS macro
expands. */
#define FRA_REG(X,MODE,OPNUM,TYPE) \
do { \
rtx tem = make_memloc ((X), REGNO (X)); \
\
if (! strict_memory_address_p (GET_MODE (tem), XEXP (tem, 0))) \
{ \
/* Note that we're doing address in address - cf. ADDR_TYPE */ \
find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), \
&XEXP (tem, 0), (OPNUM), \
ADDR_TYPE (TYPE), ind_levels, insn); \
} \
(X) = tem; \
} while (0)
/* For the IP2K, we want to be clever about picking IP vs DP for a
base pointer since IP only directly supports a zero displacement.
(Note that we have modified all the HI patterns to correctly handle
IP references by manipulating iph:ipl as we fetch the pieces). */
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND,WIN) \
{ \
if (GET_CODE (X) == PLUS \
&& REG_P (XEXP (X, 0)) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT) \
{ \
int disp = INTVAL (XEXP (X, 1)); \
int fit = (disp >= 0 && disp <= (127 - 2 * GET_MODE_SIZE (MODE))); \
rtx reg = XEXP (X, 0); \
if (!fit) \
{ \
push_reload ((X), NULL_RTX, &(X), \
NULL, MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
VOIDmode, 0, 0, OPNUM, TYPE); \
goto WIN; \
} \
if (reg_equiv_memory_loc[REGNO (reg)] \
&& (reg_equiv_address[REGNO (reg)] || num_not_at_initial_offset)) \
{ \
rtx mem = make_memloc (reg, REGNO (reg)); \
if (! strict_memory_address_p (GET_MODE (mem), XEXP (mem, 0))) \
{ \
/* Note that we're doing address in address - cf. ADDR_TYPE */\
find_reloads_address (GET_MODE (mem), &mem, XEXP (mem, 0), \
&XEXP (mem, 0), (OPNUM), \
ADDR_TYPE (TYPE), (IND), insn); \
} \
push_reload (mem, NULL, &XEXP (X, 0), NULL, \
GENERAL_REGS, Pmode, VOIDmode, 0, 0, \
OPNUM, TYPE); \
push_reload (X, NULL, &X, NULL, \
MODE_BASE_REG_CLASS (MODE), GET_MODE (X), VOIDmode, \
0, 0, OPNUM, TYPE); \
goto WIN; \
} \
} \
}
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
do { \
if (ip2k_mode_dependent_address (ADDR)) goto LABEL; \
} while (0)
#define LEGITIMATE_CONSTANT_P(X) 1
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 7
#define MEMORY_MOVE_COST(MODE,CLASS,IN) 6
#define SLOW_BYTE_ACCESS 0
#define NO_FUNCTION_CSE
#define TEXT_SECTION_ASM_OP ".text"
#define DATA_SECTION_ASM_OP ".data"
#define JUMP_TABLES_IN_TEXT_SECTION 1
#define ASM_COMMENT_START " ; "
#define ASM_APP_ON "/* #APP */\n"
#define ASM_APP_OFF "/* #NOAPP */\n"
#define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
fprintf ((STREAM), ".double %.20e\n", (VALUE))
#define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
asm_output_float ((STREAM), (VALUE))
#define ASM_OUTPUT_INT(FILE, VALUE) \
( fprintf ((FILE), "\t.long "), \
output_addr_const ((FILE), (VALUE)), \
fputs ("\n", (FILE)))
#define ASM_OUTPUT_SHORT(FILE,VALUE) \
asm_output_short ((FILE), (VALUE))
#define ASM_OUTPUT_CHAR(FILE,VALUE) \
asm_output_char ((FILE), (VALUE))
#define ASM_OUTPUT_BYTE(FILE,VALUE) \
asm_output_byte ((FILE), (VALUE))
#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) \
((C) == '\n' || ((C) == '$'))
#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
do { \
fputs ("\t.comm ", (STREAM)); \
assemble_name ((STREAM), (NAME)); \
fprintf ((STREAM), ",%d\n", (int)(SIZE)); \
} while (0)
#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
do { \
fputs ("\t.lcomm ", (STREAM)); \
assemble_name ((STREAM), (NAME)); \
fprintf ((STREAM), ",%d\n", (int)(SIZE)); \
} while (0)
#undef WEAK_ASM_OP
#define WEAK_ASM_OP ".weak"
#undef ASM_DECLARE_FUNCTION_SIZE
#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
do { \
if (!flag_inhibit_size_directive) \
ASM_OUTPUT_MEASURED_SIZE (FILE, FNAME); \
} while (0)
#define ESCAPES \
"\1\1\1\1\1\1\1\1btn\1fr\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
\0\0\"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\\0\0\0\
\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\1\
\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1"
/* A table of bytes codes used by the ASM_OUTPUT_ASCII and
ASM_OUTPUT_LIMITED_STRING macros. Each byte in the table
corresponds to a particular byte value [0..255]. For any
given byte value, if the value in the corresponding table
position is zero, the given character can be output directly.
If the table value is 1, the byte must be output as a \ooo
octal escape. If the tables value is anything else, then the
byte value should be output as a \ followed by the value
in the table. Note that we can use standard UN*X escape
sequences for many control characters, but we don't use
\a to represent BEL because some svr4 assemblers (e.g. on
the i386) don't know about that. Also, we don't use \v
since some versions of gas, such as 2.2 did not accept it. */
/* Globalizing directive for a label. */
#define GLOBAL_ASM_OP ".global\t"
#define REGISTER_NAMES { \
"$00","$01","$02","$03","iph","ipl","sph","spl", \
"pch","pcl","wreg","status","dph","dpl","$0e","mulh", \
"$10","$11","$12","$13","$14","$15","$16","$17", \
"$18","$19","$1a","$1b","$1c","$1d","$1e","$1f", \
"$20","$21","$22","$23","$24","$25","$26","$27", \
"$28","$29","$2a","$2b","$2c","$2d","$2e","$2f", \
"$30","$31","$32","$33","$34","$35","$36","$37", \
"$38","$39","$3a","$3b","$3c","$3d","$3e","$3f", \
"$40","$41","$42","$43","$44","$45","$46","$47", \
"$48","$49","$4a","$4b","$4c","$4d","$4e","$4f", \
"$50","$51","$52","$53","$54","$55","$56","$57", \
"$58","$59","$5a","$5b","$5c","$5d","$5e","$5f", \
"$60","$61","$62","$63","$64","$65","$66","$67", \
"$68","$69","$6a","$6b","$6c","$6d","$6e","$6f", \
"$70","$71","$72","$73","$74","$75","$76","$77", \
"$78","$79","$7a","$7b","$7c","$7d","callh","calll", \
"$80","$81","$82","$83","$84","$85","$86","$87", \
"$88","$89","$8a","$8b","$8c","$8d","$8e","$8f", \
"$90","$91","$92","$93","$94","$95","$96","$97", \
"$98","$99","$9a","$9b","$9c","$9d","$9e","$9f", \
"$a0","$a1","$a2","$a3","$a4","$a5","$a6","$a7", \
"$a8","$a9","$aa","$ab","$ac","$ad","$ae","$af", \
"$b0","$b1","$b2","$b3","$b4","$b5","$b6","$b7", \
"$b8","$b9","$ba","$bb","$bc","$bd","$be","$bf", \
"$c0","$c1","$c2","$c3","$c4","$c5","$c6","$c7", \
"$c8","$c9","$ca","$cb","$cc","$cd","$ce","$cf", \
"$d0","$d1","$d2","$d3","$d4","$d5","$d6","$d7", \
"$d8","$d9","$da","$db","$dc","$dd","$de","$df", \
"$e0","$e1","$e2","$e3","$e4","$e5","$e6","$e7", \
"$e8","$e9","$ea","$eb","$ec","$ed","$ee","$ef", \
"$f0","$f1","$f2","$f3","$f4","$f5","$f6","$f7", \
"$f8","$f9","$fa","$fb","$fc","$fd","$fe","$ff", \
"vfph","vfpl","vaph","vapl"}
#define PRINT_OPERAND(STREAM, X, CODE) \
print_operand ((STREAM), (X), (CODE))
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '<' || (CODE) == '>')
#define PRINT_OPERAND_ADDRESS(STREAM, X) print_operand_address(STREAM, X)
/* Since register names don't have a prefix, we must preface all
user identifiers with the '_' to prevent confusion. */
#undef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX "_"
#define LOCAL_LABEL_PREFIX ".L"
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
asm_fprintf ((STREAM), "\tpage\t%L%d\n\tjmp\t%L%d\n", (VALUE), (VALUE))
/* elfos.h presumes that we will want switch/case dispatch tables aligned.
This is not so for the ip2k. */
#undef ASM_OUTPUT_CASE_LABEL
#undef ASM_OUTPUT_ADDR_VEC_ELT
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
asm_fprintf ((STREAM), "\tpage\t%L%d\n\tjmp\t%L%d\n", (VALUE), (VALUE))
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
fprintf ((STREAM), "\t.align %d\n", (POWER))
/* Since instructions are 16 bit word addresses, we should lie and claim that
the dispatch vectors are in QImode. Otherwise the offset into the jump
table will be scaled by the MODE_SIZE. */
#define CASE_VECTOR_MODE QImode
#undef WORD_REGISTER_OPERATIONS
#define MOVE_MAX 1
#define MOVE_RATIO 3
/* MOVE_RATIO is the number of move instructions that is better than a
block move. Make this small on the IP2k, since the code size grows very
large with each move. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define Pmode HImode
#define FUNCTION_MODE HImode
#define DOLLARS_IN_IDENTIFIERS 0
extern int ip2k_reorg_in_progress;
/* Flag if we're in the middle of IP2k-specific reorganization. */
extern int ip2k_reorg_completed;
/* Flag if we've completed our IP2k-specific reorganization. If we have
then we allow quite a few more tricks than before. */
extern int ip2k_reorg_split_dimode;
extern int ip2k_reorg_split_simode;
extern int ip2k_reorg_split_qimode;
extern int ip2k_reorg_split_himode;
/* Flags for various split operations that we run in sequence. */
extern int ip2k_reorg_merge_qimode;
/* Flag to indicate that it's safe to merge QImode operands. */
#define TRAMPOLINE_TEMPLATE(FILE) abort ()
#define TRAMPOLINE_SIZE 4
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
emit_move_insn (gen_rtx_MEM (HImode, plus_constant ((TRAMP), 2)), \
CXT); \
emit_move_insn (gen_rtx_MEM (HImode, plus_constant ((TRAMP), 6)), \
FNADDR); \
}
/* Store in cc_status the expressions
that the condition codes will describe
after execution of an instruction whose pattern is EXP.
Do not alter them if the instruction would not alter the cc's. */
#define NOTICE_UPDATE_CC(EXP, INSN) (void)(0)
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. */
#define FUNCTION_PROFILER(FILE, LABELNO) \
fprintf ((FILE), "/* profiler %d */", (LABELNO))
#undef ENDFILE_SPEC
#undef LINK_SPEC
#undef STARTFILE_SPEC
#if defined(__STDC__) || defined(ALMOST_STDC)
#define AS2(a,b,c) #a "\t" #b "," #c
#define AS1(a,b) #a "\t" #b
#else
#define AS1(a,b) "a b"
#define AS2(a,b,c) "a b,c"
#endif
#define OUT_AS1(a,b) output_asm_insn (AS1 (a,b), operands)
#define OUT_AS2(a,b,c) output_asm_insn (AS2 (a,b,c), operands)
#define CR_TAB "\n\t"
#define PREDICATE_CODES \
{"ip2k_ip_operand", {MEM}}, \
{"ip2k_short_operand", {MEM}}, \
{"ip2k_gen_operand", {MEM, REG, SUBREG}}, \
{"ip2k_nonptr_operand", {REG, SUBREG}}, \
{"ip2k_ptr_operand", {REG, SUBREG}}, \
{"ip2k_split_dest_operand", {REG, SUBREG, MEM}}, \
{"ip2k_sp_operand", {REG}}, \
{"ip2k_nonsp_reg_operand", {REG, SUBREG}}, \
{"ip2k_symbol_ref_operand", {SYMBOL_REF}}, \
{"ip2k_binary_operator", {PLUS, MINUS, MULT, DIV, \
UDIV, MOD, UMOD, AND, IOR, \
XOR, COMPARE, ASHIFT, \
ASHIFTRT, LSHIFTRT}}, \
{"ip2k_unary_operator", {NEG, NOT, SIGN_EXTEND, \
ZERO_EXTEND}}, \
{"ip2k_unsigned_comparison_operator", {LTU, GTU, NE, \
EQ, LEU, GEU}},\
{"ip2k_signed_comparison_operator", {LT, GT, LE, GE}},
#define DWARF2_DEBUGGING_INFO 1
#define DWARF2_ASM_LINE_DEBUG_INFO 1
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
/* Miscellaneous macros to describe machine specifics. */
#define IS_PSEUDO_P(R) (REGNO (R) >= FIRST_PSEUDO_REGISTER)
/* Default calculations would cause DWARF address sizes to be 2 bytes,
but the Harvard architecture of the IP2k and the word-addressed 64k
of instruction memory causes us to want a 32-bit "address" field. */
#undef DWARF2_ADDR_SIZE
#define DWARF2_ADDR_SIZE 4

6903
gcc/config/ip2k/ip2k.md
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File diff suppressed because it is too large Load Diff

1516
gcc/config/ip2k/libgcc.S
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File diff suppressed because it is too large Load Diff

49
gcc/config/ip2k/t-ip2k
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@ -1,49 +0,0 @@
LIB1ASMSRC = ip2k/libgcc.S
LIB1ASMFUNCS = \
_indcall \
_mulhi3 \
_mulsi3 \
_muldi3 \
_udivmodhi4 \
_divmodhi4 \
_udivmodsi4 \
_divmodsi4 \
_udivmoddi4 \
_divmoddi4 \
_cmpqi2 \
_cmphi2 \
_cmpsi2 \
_cmpdi2 \
_cmpdi2_dp \
_fp_pop_args_ret \
_pop2_args_ret \
_leaf_fp_pop_args_ret \
_movmemhi_countqi \
_movmemhi_counthi \
abort \
_exit
# libgcc2.h thinks that nobody would have SI mode when
# MIN_UNITS_PER_WORD == 1, so lie to keep from major compiler errors.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -DDF=SF -g -DMIN_UNITS_PER_WORD=2
fp-bit.c: $(srcdir)/config/fp-bit.c $(srcdir)/config/ip2k/t-ip2k crt0.o
echo '#define FLOAT' > fp-bit.c
echo '#define FLOAT_ONLY' >> fp-bit.c
echo '#define DF SF' >> fp-bit.c
echo '#define DI SI' >> fp-bit.c
echo '#define CMPtype QItype' >> fp-bit.c
echo '#define SMALL_MACHINE' >> fp-bit.c
echo 'typedef int QItype __attribute__ ((mode (QI)));' >> fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
FPBIT = fp-bit.c
# Our crt0 is written in assembler and we don't really support profiling.
CRT0_S = $(srcdir)/config/ip2k/crt0.S
MCRT0_S = $(CRT0_S)

97
gcc/config/ns32k/NOTES
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@ -1,97 +0,0 @@
Copyright (C) 2002
Free Software Foundation, Inc.
Implementation Notes
====================
IEEE floating point comparisons
Ian Dall <ian@beware.dropbear.id.au>
------------------------------------
The ns32x81 fpu handles most operands in hardware, but traps on NaN,
Inf and Denormalized numbers. The correct behavior can be handled by
the trap handler. This is mostly transparent to the compiler, but in
the case of floating point comparisons, the trap handler and the
compiler must co-operate.
Comparing a Nan with anything (including another Nan) is an unordered
comparison and a NE test should be true and any other test should be
false. There is nothing the trap handler can do to the condition codes
to make, for example ble and bgt (the machine instructions, not the
gcc insn's) both fail.
The L flag (normally used for unsigned comparisons) is cleared by a floating
point compare. So, it is possible for the trap handler to communicate that
it has seen a NaN by setting this flag.
This can get confusing so the following documents the reasoning. There
are only 3 flags of significance, N, Z and L. In what follows AB is
the conjunction of A and B ("and") A+B is the disjunction of A and B
("or"), upper case represents true and lower case represents false. So
"Zl" is "Z AND (NOT L)".
Also, we can require that the trap handler clears N and Z, whenever it
sets L. This means that in many cases, we do not need to test if L is
set or clear. The operations we require are:
Operator Expression Check L
GT Nl No
LT znl Yes
GE (Z+N)l No
LE nl Yes
EQ Zl No
NE z+L No
For example, the emitted code for the case of LT is
bhi 0f
blt %0
0:
which is, in effect, "branch if ordered and less than."
We also need insns for the reverse branches. These have the PC and
the label ref operands reversed. Thus the reverse bgt has a pattern:
(set (pc)
(if_then_else (gt (cc0)
(const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))
This is identical to a normal branch with the test complimented:
(set (pc)
(if_then_else (not (gt (cc0)
(const_int 0)))
(label_ref (match_operand 0 "" "")
(pc))))
Thus we need a family of (NOT cond) tests. For integers this is easy,
a reverse blt becomes bge. However, the possibility of unordered
comparison complicates the floating point case. So, we need to
compliment the above expressions, using deMorgan's theorem, for the reverse
branch:
Operator Expression Check L
RGT n+L Yes
RLT Z+N+L Yes
RGE zn+L Yes
RLE N+L Yes
REQ z+L No
RNE Zl No
For example the emitted code for the case of RLT is
bge %0
bhi %0
which is, in effect "branch if not less than and not unordered."
These extra comparisons are safe if the trap handler doesn't set the
L flag, since in that case the additional "bhi" instructions are never
taken. Also, these extra branch instructions are controlled by the
"-mieee-compare" option.

68
gcc/config/ns32k/STATUS
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@ -1,68 +0,0 @@
NS32K Port Status Last updated 19 Dec 2002
Recent development of the ns32k port has been as a cross compiler. As
such a native bootstrap has not been performed. Currently the
compiler successfully builds a NetBSD kernel and has been tested on
the testsuite with "make check" configured to remotely execute
tests on a pc532-netbsd.
There are a few remaining failures in the testsuite, none of which
result in incorrect code generation or unexpected ICEs.
Here follows comments on the outstanding testsuite failures:
gcc.c-torture/compile/20001226-1.c, -Os
This typically fails due to a time out or exhausting available memory.
In the past it has been found to eventually compile in under 6
minutes, with consuming up to 90MB. The timeout in dejagnu is 5
minutes.
gcc.c-torture/execute/builtin-constant.c
I don't understand why this fails. Looking at the generated assembler,
the first invocation of btest returns "1" and the second "0". Presumably
the flow analysis is meant to indicate this is a "builtin constant".
The documentation for __builtin_constant says it is allowed to fail if the
compiler can't deduce that something is a constant, so the compiler is
correct if not ideal.
gcc.dg/debug/debug-1.c scan-assembler xyzzy:
At -O3 level of optimization, variable xyzzy gets eliminated. Isn't it
reasonable that the debugging info is gone too? Indeed, the
documentation says this is expected behavior.
gcc.dg/debug/debug-2.c scan-assembler xyzzy:
As for the above.
gcc.dg/20010912-1.c
PIC is supported for the compiler, but we get a link error until we get a
cross linker which can handle dynamic linking.
gcc.dg/20020304-1.c -O -fssa -fssa-ccp
ICE -fssa and -fssa-ccp are "experimental" options. Assume not a
backend problem.
gcc.dg/20021014-1.c (test for excess errors)
This is a test of the "-p" option. Fails due to lack of mcrt0.o. This
platform support "-pg" but not "-p"
gcc.dg/20021018-1.c (test for excess errors)
Fail due to lack of dynamic link support at link time.
gcc.dg/bitfld-3.c (test for excess errors)
Execution passes, but compilation produces excessive warnings. These warnings
actually seem reasonable. The code uses __attribute__((aligned (8)), and
the maximum alignment which makes any sense for this architecture is 4.
gcc.dg/duff-2.c (test for excess errors)
Execution passes, but compilation produces excessive warnings. Doesn't look
like a backend problem.
gcc.dg/uninit-A.c -O2 -Wall -S
Bogus warnings, almost certainly not backend.
gcc.dg/special/weak-1.c execution test
X This fails for i386 too. I don't understand what the correct behavior
for this test is.
gcc.dg/special/gcsec-1.c (test for excess errors)
a.out deficiency. -ffunction-sections and -fdata-sections not supported.

34
gcc/config/ns32k/__unorddf2.c
View File

@ -1,34 +0,0 @@
/* Lightweight function to test for ieee unordered comparison
Copyright (C) 2002
Free Software Foundation, Inc.
Contributed by Ian Dall <ian@beware.dropbear.id.au>
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
# define ISNAN(x) ( \
{ \
union u { double d; unsigned int i[2]; } *t = (union u *)&(x); \
((t->i[1] & 0x7ff00000) == 0x7ff00000) && \
(t->i[0] != 0 || (t->i[1] & 0xfffff) != 0); \
})
int __unorddf2 (double, double);
int __unorddf2 (double a, double b)
{
return ISNAN(a) || ISNAN(b);
}

34
gcc/config/ns32k/__unordsf2.c
View File

@ -1,34 +0,0 @@
/* Lightweight function to test for ieee unordered comparison
Copyright (C) 2002
Free Software Foundation, Inc.
Contributed by Ian Dall <ian@beware.dropbear.id.au>
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
# define ISNAN(x) ( \
{ \
union u { float f; unsigned int i; } *t = (union u *)&(x); \
((t->i & 0x7f800000) == 0x7f800000) && \
((t->i & 0x7fffff) != 0); \
})
int __unordsf2 ( float, float);
int __unordsf2 ( float a, float b)
{
return ISNAN(a) || ISNAN(b);
}

109
gcc/config/ns32k/netbsd.h
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@ -1,109 +0,0 @@
/* Configuration for a ns32532 running NetBSD as the target machine.
Copyright (C) 1988, 1994, 1995, 1996, 1998, 2002, 2004, 2005
Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
NETBSD_OS_CPP_BUILTINS_AOUT(); \
builtin_define ("__ns32k__"); \
} \
while (0)
/* Compile for the floating point unit & 32532 by default;
Don't assume SB is zero;
Don't use bit-field instructions;
FPU is 32381;
Use multiply-add instructions */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_32532 | MASK_32381 | MASK_IEEE_COMPARE | MASK_MULT_ADD)
/* 32-bit alignment for efficiency */
#undef POINTER_BOUNDARY
#define POINTER_BOUNDARY 32
/* 32-bit alignment for efficiency */
#undef FUNCTION_BOUNDARY
#define FUNCTION_BOUNDARY 32
/* 32532 spec says it can handle any alignment. Rumor from tm-ns32k.h
tells this might not be actually true (but it's for 32032, perhaps
National has fixed the bug for 32532). You might have to change this
if the bug still exists. */
#undef STRICT_ALIGNMENT
#define STRICT_ALIGNMENT 0
/* Use pc relative addressing whenever possible,
it's more efficient than absolute (ns32k.c)
You have to fix a bug in gas 1.38.1 to make this work with gas,
patch available from jkp@cs.hut.fi.
(NetBSD's gas version has this patch already applied) */
#define PC_RELATIVE
/* Operand of bsr or jsr should be just the address. */
#define CALL_MEMREF_IMPLICIT
/* movd insns may have floating point constant operands. */
#define MOVD_FLOAT_OK
/* Define a CPP_SPEC appropriate for NetBSD. */
#undef CPP_SPEC
#define CPP_SPEC NETBSD_CPP_SPEC
/* Make gcc agree with <machine/ansi.h> */
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "int"
/* This is BSD, so it wants DBX format. */
#define DBX_DEBUGGING_INFO 1
/* Do not break .stabs pseudos into continuations. */
#define DBX_CONTIN_LENGTH 0
/* This is the char to use for continuation (in case we need to turn
continuation back on). */
#define DBX_CONTIN_CHAR '?'
/* Don't default to pcc-struct-return, because gcc is the only compiler, and
we want to retain compatibility with older gcc versions. */
#undef PCC_STATIC_STRUCT_RETURN
#define DEFAULT_PCC_STRUCT_RETURN 0
/* Until they use ELF or something that handles dwarf2 unwinds
and initialization stuff better. */
#define DWARF2_UNWIND_INFO 0

46
gcc/config/ns32k/ns32k-protos.h
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@ -1,46 +0,0 @@
/* Definitions of target machine for GNU compiler. NS32000 version.
Copyright (C) 2000, 2004 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
/* Prototypes for functions in ns32k.c */
#ifdef RTX_CODE
extern enum reg_class secondary_reload_class (enum reg_class,
enum machine_mode, rtx);
extern int reg_or_mem_operand (rtx, enum machine_mode);
extern void split_di (rtx[], int, rtx[], rtx[]);
extern void expand_block_move (rtx[]);
extern int global_symbolic_reference_mentioned_p (rtx, int);
extern void print_operand (FILE *, rtx, int);
extern void print_operand_address (FILE *, rtx);
extern const char *output_move_double (rtx *);
extern const char *output_shift_insn (rtx *);
extern int symbolic_reference_mentioned_p (rtx);
extern void ns32k_notice_update_cc (rtx, rtx);
#endif /* RTX_CODE */
#ifdef TREE_CODE
extern int ns32k_return_pops_args (tree, tree, int);
#endif /* TREE_CODE */
extern int hard_regno_mode_ok (int, enum machine_mode);
extern int register_move_cost (enum reg_class, enum reg_class);
extern const char *output_move_dconst (int, const char *);

1706
gcc/config/ns32k/ns32k.c
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File diff suppressed because it is too large Load Diff

1182
gcc/config/ns32k/ns32k.h
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File diff suppressed because it is too large Load Diff

3082
gcc/config/ns32k/ns32k.md
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File diff suppressed because it is too large Load Diff

108
gcc/config/ns32k/ns32k.opt
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@ -1,108 +0,0 @@
; Options for the NS32000 port of the compiler.
; Copyright (C) 2005 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 2, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING. If not, write to the Free
; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
; 02110-1301, USA.
m32032
Target RejectNegative
Optimize for 32032
m32081
Target RejectNegative Report Mask(32081)
Use hardware fp
m32332
Target RejectNegative Report Mask(32332)
Optimize for 32332
m32381
Target RejectNegative Report Mask(32381)
Use the 32381 fpu
m32532
Target RejectNegative Report Mask(32532)
Optimize for 32532
mbitfield
Target RejectNegative Report Mask(BITFIELD)
Use bit-field instructions
mhimem
Target RejectNegative Report Mask(HIMEM)
Generate code for high memory
mieee-compare
Target RejectNegative Report Mask(IEEE_COMPARE)
Use IEEE math for fp comparisons
mmult-add
Target RejectNegative Report Mask(MULT_ADD)
Use multiply-accumulate fp instructions
mnobitfield
Target RejectNegative Report InverseMask(BITFIELD)
Do not use bit-field instructions
mnohimem
Target RejectNegative Report InverseMask(HIMEM)
Generate code for low memory
mnoieee-compare
Target RejectNegative Report InverseMask(IEEE_COMPARE)
Do not use IEEE math for fp comparisons
mnomult-add
Target RejectNegative Report InverseMask(MULT_ADD)
Do not use multiply-accumulate fp instructions
mnoregparm
Target RejectNegative Report InverseMask(REGPARM)
Pass all arguments on the stack
mnortd
Target RejectNegative Report InverseMask(RTD)
Use the normal calling convention
mnosb
Target RejectNegative Report InverseMask(SB)
Do not use register sb
mnosrc
Target RejectNegative Report InverseMask(SRC)
Do not use the 'small register classes' kludge
mregparm
Target RejectNegative Report Mask(REGPARM)
Pass some arguments in registers
mrtd
Target RejectNegative Report Mask(RTD)
Use an alternative calling convention
msb
Target RejectNegative Report Mask(SB)
Register sb is zero, use it for absolute addressing
msoft-float
Target RejectNegative
Do not use hardware fp
msrc
Target RejectNegative Report Mask(SRC)
Use the 'small register classes' kludge

4
gcc/config/ns32k/t-ns32k
View File

@ -1,4 +0,0 @@
# We want fine grained libraries, so use the new code to build the
# floating point emulation libraries.
LIB2FUNCS_EXTRA = $(srcdir)/config/ns32k/__unorddf2.c \
$(srcdir)/config/ns32k/__unordsf2.c

68
gcc/config/sparc/openbsd.h
View File

@ -1,68 +0,0 @@
/* Configuration file for sparc OpenBSD target.
Copyright (C) 1999, 2002, 2003, 2004 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
/* Target OS builtins. */
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("__unix__"); \
builtin_define ("__OpenBSD__"); \
builtin_assert ("system=unix"); \
builtin_assert ("system=OpenBSD"); \
} \
while (0)
/* Layout of source language data types */
/* This must agree with <machine/ansi.h> */
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "int"
#undef WCHAR_TYPE
#define WCHAR_TYPE "int"
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 32
/* Specific options for DBX Output. */
/* This is BSD, so it wants DBX format. */
#define DBX_DEBUGGING_INFO 1
/* This is the char to use for continuation */
#define DBX_CONTIN_CHAR '?'
/* Stack & calling: aggregate returns. */
/* Don't default to pcc-struct-return, because gcc is the only compiler, and
we want to retain compatibility with older gcc versions. */
#undef DEFAULT_PCC_STRUCT_RETURN
#define DEFAULT_PCC_STRUCT_RETURN 0
/* Assembler format: exception region output. */
/* All configurations that don't use elf must be explicit about not using
dwarf unwind information. */
#define DWARF2_UNWIND_INFO 0
#undef ASM_PREFERRED_EH_DATA_FORMAT

5
gcc/config/sparc/t-openbsd
View File

@ -1,5 +0,0 @@
# The native linker doesn't handle linking -fpic code with -fPIC code. Ugh.
# We cope by building both variants of libgcc.
MULTILIB_OPTIONS = fpic/fPIC
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib

12
gcc/doc/install.texi
View File

@ -2244,8 +2244,6 @@ GNU Compiler Collection on your machine.
@item
@uref{#x-ibm-aix,,*-ibm-aix*}
@item
@uref{#ip2k-x-elf,,ip2k-*-elf}
@item
@uref{#iq2000-x-elf,,iq2000-*-elf}
@item
@uref{#m32r-x-elf,,m32r-*-elf}
@ -3175,16 +3173,6 @@ both Power or PowerPC processors.
A default can be specified with the @option{-mcpu=@var{cpu_type}}
switch and using the configure option @option{--with-cpu-@var{cpu_type}}.
@html
<hr />
@end html
@heading @anchor{ip2k-x-elf}ip2k-*-elf
Ubicom IP2022 micro controller.
This configuration is intended for embedded systems.
There are no standard Unix configurations.
Use @samp{configure --target=ip2k-elf --enable-languages=c} to configure GCC@.
@html
<hr />
@end html

149
gcc/doc/invoke.texi
View File

@ -599,12 +599,6 @@ Objective-C and Objective-C++ Dialects}.
-mam33-2 -mno-am33-2 @gol
-mno-crt0 -mrelax}
@emph{NS32K Options}
@gccoptlist{-m32032 -m32332 -m32532 -m32081 -m32381 @gol
-mmult-add -mnomult-add -msoft-float -mrtd -mnortd @gol
-mregparam -mnoregparam -msb -mnosb @gol
-mbitfield -mnobitfield -mhimem -mnohimem}
@emph{PDP-11 Options}
@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
-mbcopy -mbcopy-builtin -mint32 -mno-int16 @gol
@ -6970,7 +6964,6 @@ platform.
* MIPS Options::
* MMIX Options::
* MN10300 Options::
* NS32K Options::
* PDP-11 Options::
* PowerPC Options::
* RS/6000 and PowerPC Options::
@ -10407,148 +10400,6 @@ has an effect when used on the command line for the final link step.
This option makes symbolic debugging impossible.
@end table
@node NS32K Options
@subsection NS32K Options
@cindex NS32K options
These are the @samp{-m} options defined for the 32000 series. The default
values for these options depends on which style of 32000 was selected when
the compiler was configured; the defaults for the most common choices are
given below.
@table @gcctabopt
@item -m32032
@itemx -m32032
@opindex m32032
@opindex m32032
Generate output for a 32032. This is the default
when the compiler is configured for 32032 and 32016 based systems.
@item -m32332
@itemx -m32332
@opindex m32332
@opindex m32332
Generate output for a 32332. This is the default
when the compiler is configured for 32332-based systems.
@item -m32532
@itemx -m32532
@opindex m32532
@opindex m32532
Generate output for a 32532. This is the default
when the compiler is configured for 32532-based systems.
@item -m32081
@opindex m32081
Generate output containing 32081 instructions for floating point.
This is the default for all systems.
@item -m32381
@opindex m32381
Generate output containing 32381 instructions for floating point. This
also implies @option{-m32081}. The 32381 is only compatible with the 32332
and 32532 cpus. This is the default for the pc532-netbsd configuration.
@item -mmulti-add
@opindex mmulti-add
Try and generate multiply-add floating point instructions @code{polyF}
and @code{dotF}. This option is only available if the @option{-m32381}
option is in effect. Using these instructions requires changes to
register allocation which generally has a negative impact on
performance. This option should only be enabled when compiling code
particularly likely to make heavy use of multiply-add instructions.
@item -mnomulti-add
@opindex mnomulti-add
Do not try and generate multiply-add floating point instructions
@code{polyF} and @code{dotF}. This is the default on all platforms.
@item -msoft-float
@opindex msoft-float
Generate output containing library calls for floating point.
@strong{Warning:} the requisite libraries may not be available.
@item -mieee-compare
@itemx -mno-ieee-compare
@opindex mieee-compare
@opindex mno-ieee-compare
Control whether or not the compiler uses IEEE floating point
comparisons. These handle correctly the case where the result of a
comparison is unordered.
@strong{Warning:} the requisite kernel support may not be available.
@item -mnobitfield
@opindex mnobitfield
Do not use the bit-field instructions. On some machines it is faster to
use shifting and masking operations. This is the default for the pc532.
@item -mbitfield
@opindex mbitfield
Do use the bit-field instructions. This is the default for all platforms
except the pc532.
@item -mrtd
@opindex mrtd
Use a different function-calling convention, in which functions
that take a fixed number of arguments return pop their
arguments on return with the @code{ret} instruction.
This calling convention is incompatible with the one normally
used on Unix, so you cannot use it if you need to call libraries
compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including @code{printf});
otherwise incorrect code will be generated for calls to those
functions.
In addition, seriously incorrect code will result if you call a
function with too many arguments. (Normally, extra arguments are
harmlessly ignored.)
This option takes its name from the 680x0 @code{rtd} instruction.
@item -mregparam
@opindex mregparam
Use a different function-calling convention where the first two arguments
are passed in registers.
This calling convention is incompatible with the one normally
used on Unix, so you cannot use it if you need to call libraries
compiled with the Unix compiler.
@item -mnoregparam
@opindex mnoregparam
Do not pass any arguments in registers. This is the default for all
targets.
@item -msb
@opindex msb
It is OK to use the sb as an index register which is always loaded with
zero. This is the default for the pc532-netbsd target.
@item -mnosb
@opindex mnosb
The sb register is not available for use or has not been initialized to
zero by the run time system. This is the default for all targets except
the pc532-netbsd. It is also implied whenever @option{-mhimem} or
@option{-fpic} is set.
@item -mhimem
@opindex mhimem
Many ns32000 series addressing modes use displacements of up to 512MB@.
If an address is above 512MB then displacements from zero can not be used.
This option causes code to be generated which can be loaded above 512MB@.
This may be useful for operating systems or ROM code.
@item -mnohimem
@opindex mnohimem
Assume code will be loaded in the first 512MB of virtual address space.
This is the default for all platforms.
@end table
@node PDP-11 Options
@subsection PDP-11 Options
@cindex PDP-11 Options

70
gcc/doc/md.texi
View File

@ -2165,76 +2165,6 @@ An integer constant with all bits set except exactly one.
Any SYMBOL_REF.
@end table
@item IP2K---@file{ip2k.h}
@table @code
@item a
@samp{DP} or @samp{IP} registers (general address)
@item f
@samp{IP} register
@item j
@samp{IPL} register
@item k
@samp{IPH} register
@item b
@samp{DP} register
@item y
@samp{DPH} register
@item z
@samp{DPL} register
@item q
@samp{SP} register
@item c
@samp{DP} or @samp{SP} registers (offsettable address)
@item d
Non-pointer registers (not @samp{SP}, @samp{DP}, @samp{IP})
@item u
Non-SP registers (everything except @samp{SP})
@item R
Indirect through @samp{IP}---Avoid this except for @code{QImode}, since we
can't access extra bytes
@item S
Indirect through @samp{SP} or @samp{DP} with short displacement (0..127)
@item T
Data-section immediate value
@item I
Integers from @minus{}255 to @minus{}1
@item J
Integers from 0 to 7---valid bit number in a register
@item K
Integers from 0 to 127---valid displacement for addressing mode
@item L
Integers from 1 to 127
@item M
Integer @minus{}1
@item N
Integer 1
@item O
Zero
@item P
Integers from 0 to 255
@end table
@item MIPS---@file{mips.h}
@table @code
@item d

5
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2005-07-20 Kazu Hirata <kazu@codesourcery.com>
* gcc.dg/20020312-2.c, gcc.dg/sibcall-3.c, gcc.dg/sibcall-4.c,
gcc.dg/cpp/assert4.c: Don't mention obsolete ports.
2005-07-19 James A. Morrison <phython@gcc.gnu.org>
* gcc.dg/fold-abs-1.c: New test.

2
gcc/testsuite/gcc.dg/20020312-2.c
View File

@ -44,8 +44,6 @@ extern void abort (void);
/* No pic register. */
#elif defined(__mn10300__)
/* No pic register. */
#elif #cpu(ns32k)
/* No pic register. */
#elif defined(__hppa__)
/* PIC register is %r27 or %r19, but is used even without -fpic. */
#elif defined(__pdp11__)

16
gcc/testsuite/gcc.dg/cpp/assert4.c
View File

@ -254,14 +254,6 @@
# error
#endif
#if defined __i860__
# if !#cpu(i860) || !#machine(i860)
# error
# endif
#elif #cpu(i860) || #machine(i860)
# error
#endif
#if defined __ia64__
# if !#cpu(ia64) || !#machine(ia64)
# error
@ -319,14 +311,6 @@
# error
#endif
#if defined __ns32k__
# if !#cpu(ns32k) || !#machine(ns32k)
# error
# endif
#elif #cpu(ns32k) || #machine(ns32k)
# error
#endif
#if defined __pdp11__
# if !#cpu(pdp11) || !#machine(pdp11)
# error

2
gcc/testsuite/gcc.dg/sibcall-3.c
View File

@ -5,7 +5,7 @@
Copyright (C) 2002 Free Software Foundation Inc.
Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* ip2k-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* ns32k-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
/* { dg-options "-O2 -foptimize-sibling-calls" } */
/* The option -foptimize-sibling-calls is the default, but serves as

2
gcc/testsuite/gcc.dg/sibcall-4.c
View File

@ -5,7 +5,7 @@
Copyright (C) 2002 Free Software Foundation Inc.
Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* ip2k-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* ns32k-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
/* { dg-options "-O2 -foptimize-sibling-calls" } */
/* The option -foptimize-sibling-calls is the default, but serves as