mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-04-05 13:51:00 +08:00
Code Issues Packages Projects Releases Wiki Activity

(cmphi): Fixed when next CC user is unsigned.

Browse Source 
(mov[hq]i-[23]): New patterns for mem-indirect moves.
(movhf,movtqf): Corrected.

From-SVN: r13963
This commit is contained in:
Richard Kenner 1997-04-23 09:47:27 -04:00
parent 31c21e0c02
commit fd07302117
1 changed files with 82 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

87
gcc/config/1750a/1750a.md
View File

@ -195,9 +195,21 @@
(compare (match_operand:HI 0 "general_operand" "r,r")
(match_operand:HI 1 "general_operand" "r,m")))]
""
"@
dcr r%0,r%1
dc r%0,%1 ")
"*
{
if (next_cc_user_is_unsigned (insn))
{
if (which_alternative == 0)
return \"ducr.m %0,%1\";
return \"duc.m %0,%1\";
}
else
{
if (which_alternative == 0)
return \"dcr r%0,r%1\";
return \"dc r%0,%1\";
}
} ")
(define_insn "cmphf"
[(set (cc0)
@ -317,6 +329,23 @@
;; 16-bit moves
; memory indirect to reg
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
(mem:QI (match_operand 1 "memory_operand" "m")))]
""
"li r%0,%1")
; reg/const to memory indirect
(define_insn ""
[(set (mem:QI (match_operand 0 "memory_operand" "=m,m"))
(match_operand:QI 1 "nonmemory_operand" "r,K"))]
""
"@
sti r%1,%0
stci %1,%0")
; general case
(define_insn "movqi"
[(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,m,m")
(match_operand:QI 1 "general_operand" "O,I,J,i,r,m,r,K"))]
@ -333,6 +362,21 @@
;; 32-bit moves
; memory indirect to reg
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(mem:HI (match_operand 1 "memory_operand" "m")))]
""
"dli r%0,%1")
; reg to memory indirect
(define_insn ""
[(set (mem:HI (match_operand 0 "memory_operand" "=m"))
(match_operand:HI 1 "register_operand" "r"))]
""
"dsti r%1,%0")
; general case
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=r,r,r,r,r,m,m")
(match_operand:HI 1 "general_operand" "O,I,J,r,m,r,K"))]
@ -368,7 +412,7 @@
;; Single-Float moves
(define_insn "movhf"
(define_insn ""
[(set (match_operand:HF 0 "general_operand" "=r,r,m,m")
(match_operand:HF 1 "general_operand" "r,m,r,G"))]
""
@ -378,10 +422,27 @@
dst r%1,%0
stc 0,%0 \;stc 0,%A0 ")
(define_expand "movhf"
[(set (match_operand:HF 0 "general_operand" "")
(match_operand:HF 1 "general_operand" ""))]
""
"
{
enum rtx_code op1code = GET_CODE (operands[1]);
if (GET_CODE (operands[0]) == MEM)
{
if (op1code == MEM || (op1code == CONST_DOUBLE
&& !rtx_equal_p (operands[1], CONST0_RTX (HFmode))))
operands[1] = force_reg (HFmode, operands[1]);
}
else if (op1code == CONST_DOUBLE)
operands[1] = force_const_mem (HFmode, operands[1]);
}")
;; Longfloat moves
(define_insn "movtqf"
(define_insn ""
[(set (match_operand:TQF 0 "general_operand" "=r,r,m")
(match_operand:TQF 1 "general_operand" "r,m,r"))]
""
@ -390,6 +451,22 @@
efl r%0,%1
efst r%1,%0 ")
(define_expand "movtqf"
[(set (match_operand:TQF 0 "general_operand" "")
(match_operand:TQF 1 "general_operand" ""))]
""
"
{
enum rtx_code op1code = GET_CODE (operands[1]);
if (GET_CODE (operands[0]) == MEM)
{
if (op1code == MEM || op1code == CONST_DOUBLE)
operands[1] = force_reg (TQFmode, operands[1]);
}
else if (op1code == CONST_DOUBLE)
operands[1] = force_const_mem (TQFmode, operands[1]);
}")
;; add instructions