[AArch64] Use conditional negate for abs

2015-05-14  Wilco Dijkstra  <wdijkstr@arm.com>

      gcc/
	* config/aarch64/aarch64.md (absdi2): Optimize abs expansion.
	(csneg3<mode>_insn): Enable expansion of pattern.

      gcc/testsuite/
	* gcc.target/aarch64/abs_1.c (abs64): Update test for new abs expansion.
	(abs64_in_dreg): Likewise.

From-SVN: r223197
This commit is contained in:
Wilco Dijkstra 2015-05-14 13:35:30 +00:00 committed by Jiong Wang
parent a0c4531ccf
commit fc8b587d7e
4 changed files with 19 additions and 28 deletions

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@ -1,3 +1,8 @@
2015-05-14 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.md (absdi2): Optimize abs expansion.
(csneg3<mode>_insn): Enable expansion of pattern.
2015-05-14 Nick Clifton <nickc@redhat.com>
* config/rl78/rl78.c (rl78_select_section): Select the correct

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@ -2182,34 +2182,16 @@
[(set_attr "type" "alu_ext")]
)
(define_insn_and_split "absdi2"
[(set (match_operand:DI 0 "register_operand" "=&r,w")
(abs:DI (match_operand:DI 1 "register_operand" "r,w")))]
(define_expand "abs<mode>2"
[(match_operand:GPI 0 "register_operand" "")
(match_operand:GPI 1 "register_operand" "")]
""
"@
#
abs\\t%d0, %d1"
"reload_completed
&& GP_REGNUM_P (REGNO (operands[0]))
&& GP_REGNUM_P (REGNO (operands[1]))"
[(const_int 0)]
{
emit_insn (gen_rtx_SET (operands[0],
gen_rtx_XOR (DImode,
gen_rtx_ASHIFTRT (DImode,
operands[1],
GEN_INT (63)),
operands[1])));
emit_insn (gen_rtx_SET (operands[0],
gen_rtx_MINUS (DImode,
operands[0],
gen_rtx_ASHIFTRT (DImode,
operands[1],
GEN_INT (63)))));
rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
emit_insn (gen_csneg3<mode>_insn (operands[0], x, operands[1], operands[1]));
DONE;
}
[(set_attr "type" "alu_sreg")
(set_attr "simd" "no,yes")]
)
(define_insn "neg<mode>2"
@ -2888,7 +2870,7 @@
[(set_attr "type" "csel")]
)
(define_insn "*csneg3<mode>_insn"
(define_insn "csneg3<mode>_insn"
[(set (match_operand:GPI 0 "register_operand" "=r")
(if_then_else:GPI
(match_operand 1 "aarch64_comparison_operation" "")

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@ -1,3 +1,8 @@
2015-05-14 Wilco Dijkstra <wdijkstr@arm.com>
* gcc.target/aarch64/abs_1.c (abs64): Update test for new abs expansion.
(abs64_in_dreg): Likewise.
2015-05-14 Marek Polacek <polacek@redhat.com>
PR c/66066

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@ -7,15 +7,14 @@ extern void abort (void);
long long
abs64 (long long a)
{
/* { dg-final { scan-assembler "eor\t" } } */
/* { dg-final { scan-assembler "sub\t" } } */
/* { dg-final { scan-assembler "csneg\t" } } */
return llabs (a);
}
long long
abs64_in_dreg (long long a)
{
/* { dg-final { scan-assembler "abs\td\[0-9\]+, d\[0-9\]+" } } */
/* { dg-final { scan-assembler "csneg\t" } } */
register long long x asm ("d8") = a;
register long long y asm ("d9");
asm volatile ("" : : "w" (x));