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arm.md (UNSPEC_PIC_BASE): Update documentation.
gcc/ * config/arm/arm.md (UNSPEC_PIC_BASE): Update documentation. (UNSPEC_GOTSYM_OFF): New unspec. (pic_add_dot_plus_four): Simplify the UNSPEC_PIC_BASE operands. (pic_add_dot_plus_eight): Likewise. (tls_load_dot_plus_eight): Likewise. Update peephole2. * config/arm/thumb2.md (pic_load_dot_plus_four): Simplify the UNSPEC_PIC_BASE operands. * config/arm/arm.c (arm_load_pic_register): Use UNSPEC_GOTSYM_OFF. (arm_output_addr_const_extra): Handle it. From-SVN: r141560
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
dffda765c0
commit
f9bd1a8966
@ -1,3 +1,15 @@
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2008-11-03 Richard Sandiford <rdsandiford@googlemail.com>
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* config/arm/arm.md (UNSPEC_PIC_BASE): Update documentation.
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(UNSPEC_GOTSYM_OFF): New unspec.
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(pic_add_dot_plus_four): Simplify the UNSPEC_PIC_BASE operands.
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(pic_add_dot_plus_eight): Likewise.
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(tls_load_dot_plus_eight): Likewise. Update peephole2.
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* config/arm/thumb2.md (pic_load_dot_plus_four): Simplify the
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UNSPEC_PIC_BASE operands.
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* config/arm/arm.c (arm_load_pic_register): Use UNSPEC_GOTSYM_OFF.
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(arm_output_addr_const_extra): Handle it.
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2008-11-03 Eric Botcazou <ebotcazou@adacore.com>
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* config/i386/i386.c (classify_argument) <ARRAY_TYPE>: Promote partial
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@ -3659,8 +3659,7 @@ static GTY(()) int pic_labelno;
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void
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arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
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{
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rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx, pic_reg;
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rtx global_offset_table;
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rtx l1, labelno, pic_tmp, pic_rtx, pic_reg;
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if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
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return;
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@ -3688,20 +3687,11 @@ arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
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l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
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l1 = gen_rtx_CONST (VOIDmode, l1);
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global_offset_table
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= gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
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/* On the ARM the PC register contains 'dot + 8' at the time of the
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addition, on the Thumb it is 'dot + 4'. */
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pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
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if (GOT_PCREL)
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{
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pic_tmp2 = gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx);
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pic_tmp2 = gen_rtx_CONST (VOIDmode, pic_tmp2);
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}
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else
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pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
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pic_rtx = gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp);
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pic_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4);
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pic_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, pic_rtx),
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UNSPEC_GOTSYM_OFF);
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pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
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if (TARGET_ARM)
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@ -18994,6 +18984,16 @@ arm_output_addr_const_extra (FILE *fp, rtx x)
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ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
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assemble_name_raw (fp, label);
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return TRUE;
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}
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else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOTSYM_OFF)
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{
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assemble_name (fp, "_GLOBAL_OFFSET_TABLE_");
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if (GOT_PCREL)
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fputs ("+.", fp);
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fputs ("-(", fp);
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output_addr_const (fp, XVECEXP (x, 0, 0));
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fputc (')', fp);
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return TRUE;
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}
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else if (GET_CODE (x) == CONST_VECTOR)
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@ -67,10 +67,9 @@
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(UNSPEC_PIC_SYM 3) ; A symbol that has been treated properly for pic
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; usage, that is, we will add the pic_register
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; value to it before trying to dereference it.
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(UNSPEC_PIC_BASE 4) ; Adding the PC value to the offset to the
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; GLOBAL_OFFSET_TABLE. The operation is fully
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; described by the RTL but must be wrapped to
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; prevent combine from trying to rip it apart.
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(UNSPEC_PIC_BASE 4) ; Add PC and all but the last operand together,
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; The last operand is the number of a PIC_LABEL
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; that points at the containing instruction.
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(UNSPEC_PRLG_STK 5) ; A special barrier that prevents frame accesses
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; being scheduled before the stack adjustment insn.
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(UNSPEC_PROLOGUE_USE 6) ; As USE insns are not meaningful after reload,
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@ -98,6 +97,8 @@
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; generate correct unwind information.
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(UNSPEC_PIC_OFFSET 23) ; A symbolic 12-bit OFFSET that has been treated
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; correctly for PIC usage.
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(UNSPEC_GOTSYM_OFF 24) ; The offset of the start of the the GOT from a
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; a given symbolic address.
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]
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)
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@ -5033,8 +5034,8 @@
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(define_insn "pic_add_dot_plus_four"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "0")
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(const (plus:SI (pc) (const_int 4))))
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(unspec:SI [(match_operand:SI 1 "register_operand" "0")
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(const_int 4)
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(match_operand 2 "" "")]
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UNSPEC_PIC_BASE))]
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"TARGET_THUMB1"
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@ -5048,8 +5049,8 @@
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(define_insn "pic_add_dot_plus_eight"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "r")
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(const (plus:SI (pc) (const_int 8))))
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(unspec:SI [(match_operand:SI 1 "register_operand" "r")
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(const_int 8)
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(match_operand 2 "" "")]
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UNSPEC_PIC_BASE))]
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"TARGET_ARM"
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@ -5063,8 +5064,8 @@
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(define_insn "tls_load_dot_plus_eight"
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[(set (match_operand:SI 0 "register_operand" "+r")
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(mem:SI (unspec:SI [(plus:SI (match_operand:SI 1 "register_operand" "r")
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(const (plus:SI (pc) (const_int 8))))
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(mem:SI (unspec:SI [(match_operand:SI 1 "register_operand" "r")
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(const_int 8)
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(match_operand 2 "" "")]
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UNSPEC_PIC_BASE)))]
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"TARGET_ARM"
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@ -5081,18 +5082,18 @@
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;; tls_load_dot_plus_eight by a peephole.
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(define_peephole2
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(unspec:SI [(plus:SI (match_operand:SI 3 "register_operand" "")
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(const (plus:SI (pc) (const_int 8))))]
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UNSPEC_PIC_BASE))
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(use (label_ref (match_operand 1 "" "")))])
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[(set (match_operand:SI 0 "register_operand" "")
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(unspec:SI [(match_operand:SI 3 "register_operand" "")
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(const_int 8)
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(match_operand 1 "" "")]
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UNSPEC_PIC_BASE))
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(set (match_operand:SI 2 "register_operand" "") (mem:SI (match_dup 0)))]
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"TARGET_ARM && peep2_reg_dead_p (2, operands[0])"
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[(parallel [(set (match_dup 2)
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(mem:SI (unspec:SI [(plus:SI (match_dup 3)
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(const (plus:SI (pc) (const_int 8))))]
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UNSPEC_PIC_BASE)))
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(use (label_ref (match_dup 1)))])]
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[(set (match_dup 2)
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(mem:SI (unspec:SI [(match_dup 3)
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(const_int 8)
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(match_dup 1)]
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UNSPEC_PIC_BASE)))]
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""
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)
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@ -259,8 +259,8 @@
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;; word aligned.
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(define_insn "pic_load_dot_plus_four"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(const (plus:SI (pc) (const_int 4)))
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(use (match_operand 1 "" ""))]
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(unspec:SI [(const_int 4)
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(match_operand 1 "" "")]
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UNSPEC_PIC_BASE))]
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"TARGET_THUMB2"
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"*
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