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arm.md (cmpsi2_addneg): New ARM pattern.
* arm.md (cmpsi2_addneg): New ARM pattern. Add peephole2 to generate it. (cbranchne_decr1): New Thumb pattern. * arm.c (arm_addimm_operand): New insn predicate. * arm-protos.h: Add a prototype for it. * arm.h (PREDICATE_CODES): Add it. From-SVN: r72188
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Richard Earnshaw
Richard Earnshaw
parent
79ae11c4a3
commit
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@ -1,3 +1,12 @@
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2003-10-07 Richard Earnshaw <rearnsha@arm.com>
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* arm.md (cmpsi2_addneg): New ARM pattern. Add peephole2 to generate
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it.
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(cbranchne_decr1): New Thumb pattern.
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* arm.c (arm_addimm_operand): New insn predicate.
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* arm-protos.h: Add a prototype for it.
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* arm.h (PREDICATE_CODES): Add it.
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2003-10-07 Dorit Naishlos <dorit@il.ibm.com>
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* sched-int.h (sched_info): New field
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@ -65,6 +65,7 @@ extern int arm_reload_memory_operand (rtx, enum machine_mode);
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extern int arm_rhs_operand (rtx, enum machine_mode);
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extern int arm_rhsm_operand (rtx, enum machine_mode);
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extern int arm_add_operand (rtx, enum machine_mode);
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extern int arm_addimm_operand (rtx, enum machine_mode);
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extern int arm_not_operand (rtx, enum machine_mode);
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extern int offsettable_memory_operand (rtx, enum machine_mode);
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extern int alignable_memory_operand (rtx, enum machine_mode);
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@ -3750,6 +3750,15 @@ arm_add_operand (rtx op, enum machine_mode mode)
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|| const_ok_for_arm (-INTVAL (op)))));
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}
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/* Return TRUE for valid ARM constants (or when valid if negated). */
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int
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arm_addimm_operand (rtx op, enum machine_mode mode)
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{
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return (GET_CODE (op) == CONST_INT
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&& (const_ok_for_arm (INTVAL (op))
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|| const_ok_for_arm (-INTVAL (op))));
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}
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int
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arm_not_operand (rtx op, enum machine_mode mode)
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{
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@ -2681,6 +2681,7 @@ extern int making_const_table;
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{"arm_hard_register_operand", {REG}}, \
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{"f_register_operand", {SUBREG, REG}}, \
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{"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
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{"arm_addimm_operand", {CONST_INT}}, \
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{"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
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{"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
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{"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
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@ -667,6 +667,60 @@
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[(set_attr "conds" "set")]
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)
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;; This is the canonicalization of addsi3_compare0_for_combiner when the
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;; addend is a constant.
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(define_insn "*cmpsi2_addneg"
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(match_operand:SI 1 "s_register_operand" "r,r")
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(match_operand:SI 2 "arm_addimm_operand" "I,L")))
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(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(plus:SI (match_dup 1)
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(match_operand:SI 3 "arm_addimm_operand" "L,I")))]
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"TARGET_ARM && INTVAL (operands[2]) == -INTVAL (operands[3])"
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"@
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sub%?s\\t%0, %1, %2
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add%?s\\t%0, %1, #%n2"
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[(set_attr "conds" "set")]
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)
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;; Convert the sequence
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;; sub rd, rn, #1
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;; cmn rd, #1 (equivalent to cmp rd, #-1)
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;; bne dest
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;; into
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;; subs rd, rn, #1
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;; bcs dest ((unsigned)rn >= 1)
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;; similarly for the beq variant using bcc.
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;; This is a common looping idiom (while (n--))
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(define_peephole2
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[(set (match_operand:SI 0 "s_register_operand" "")
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(plus:SI (match_operand:SI 1 "s_register_operand" "")
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(const_int -1)))
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(set (match_operand 2 "cc_register" "")
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(compare (match_dup 0) (const_int -1)))
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(set (pc)
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(if_then_else (match_operator 3 "equality_operator"
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[(match_dup 2) (const_int 0)])
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(match_operand 4 "" "")
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(match_operand 5 "" "")))]
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"TARGET_ARM && peep2_reg_dead_p (3, operands[2])"
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[(parallel[
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(set (match_dup 2)
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(compare:CC
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(match_dup 1) (const_int 1)))
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(set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
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(set (pc)
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(if_then_else (match_op_dup 3 [(match_dup 2) (const_int 0)])
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(match_dup 4)
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(match_dup 5)))]
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"operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
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operands[3] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE
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? GEU : LTU),
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VOIDmode,
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operands[2], const0_rtx);"
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)
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;; The next four insns work because they compare the result with one of
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;; the operands, and we know that the use of the condition code is
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;; either GEU or LTU, so we can use the carry flag from the addition
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@ -5192,6 +5246,108 @@
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(const_int 8))))]
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)
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(define_insn "*cbranchne_decr1"
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[(set (pc)
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(if_then_else (match_operator 3 "equality_operator"
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[(match_operand:SI 2 "s_register_operand" "l,l,1,l")
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(const_int 0)])
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(label_ref (match_operand 4 "" ""))
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(pc)))
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(set (match_operand:SI 0 "s_register_operand" "=l,?h,?m,?m")
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(plus:SI (match_dup 2) (const_int -1)))
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(clobber (match_scratch:SI 1 "=X,l,&l,&l"))]
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"TARGET_THUMB"
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"*
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{
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rtx cond[2];
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cond[0] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE
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? GEU : LTU),
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VOIDmode, NULL, NULL);
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cond[1] = operands[4];
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if (which_alternative == 0)
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output_asm_insn (\"sub\\t%0, %2, #1\", operands);
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else if (which_alternative == 1)
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{
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/* We must provide an alternative for a hi reg because reload
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cannot handle output reloads on a jump instruction, but we
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can't subtract into that. Fortunately a mov from lo to hi
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does not clobber the condition codes. */
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output_asm_insn (\"sub\\t%1, %2, #1\", operands);
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output_asm_insn (\"mov\\t%0, %1\", operands);
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}
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else
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{
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/* Similarly, but the target is memory. */
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output_asm_insn (\"sub\\t%1, %2, #1\", operands);
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output_asm_insn (\"str\\t%1, %0\", operands);
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}
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switch (get_attr_length (insn) - (which_alternative ? 2 : 0))
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{
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case 4:
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output_asm_insn (\"b%d0\\t%l1\", &cond);
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return \"\";
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case 6:
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output_asm_insn (\"b%D0\\t.LCB%=\", &cond);
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return \"b\\t%l4\\t%@long jump\\n.LCB%=:\";
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default:
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output_asm_insn (\"b%D0\\t.LCB%=\", &cond);
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return \"bl\\t%l4\\t%@far jump\\n.LCB%=:\";
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}
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}
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"
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[(set (attr "far_jump")
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(if_then_else
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(ior (and (eq (symbol_ref ("which_alternative"))
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(const_int 0))
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(eq_attr "length" "8"))
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(eq_attr "length" "10"))
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(const_string "yes")
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(const_string "no")))
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(set_attr_alternative "length"
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[
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;; Alternative 0
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(if_then_else
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(and (ge (minus (match_dup 4) (pc)) (const_int -250))
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(le (minus (match_dup 4) (pc)) (const_int 256)))
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(const_int 4)
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(if_then_else
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(and (ge (minus (match_dup 4) (pc)) (const_int -2040))
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(le (minus (match_dup 4) (pc)) (const_int 2048)))
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(const_int 6)
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(const_int 8)))
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;; Alternative 1
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(if_then_else
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(and (ge (minus (match_dup 4) (pc)) (const_int -248))
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(le (minus (match_dup 4) (pc)) (const_int 256)))
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(const_int 6)
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(if_then_else
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(and (ge (minus (match_dup 4) (pc)) (const_int -2038))
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(le (minus (match_dup 4) (pc)) (const_int 2048)))
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(const_int 8)
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(const_int 10)))
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;; Alternative 2
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(if_then_else
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(and (ge (minus (match_dup 4) (pc)) (const_int -248))
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(le (minus (match_dup 4) (pc)) (const_int 256)))
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(const_int 6)
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(if_then_else
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(and (ge (minus (match_dup 4) (pc)) (const_int -2038))
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(le (minus (match_dup 4) (pc)) (const_int 2048)))
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(const_int 8)
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(const_int 10)))
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;; Alternative 3
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(if_then_else
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(and (ge (minus (match_dup 4) (pc)) (const_int -248))
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(le (minus (match_dup 4) (pc)) (const_int 256)))
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(const_int 6)
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(if_then_else
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(and (ge (minus (match_dup 4) (pc)) (const_int -2038))
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(le (minus (match_dup 4) (pc)) (const_int 2048)))
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(const_int 8)
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(const_int 10)))])]
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)
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;; Comparison and test insns
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