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config/stormy16/stormy16.c (combine_bnp): Add code to handle zero_extension and lshiftrt insns.
config/stormy16/stormy16.c (combine_bnp): Add code to handle zero_extension and lshiftrt insns. Replace uses of XEXP(...) with either SET_DEST() or SET_SRC() where appropriate. config/stormy16.stormy16.md (bclrx3, bsetx3): New patterns to handle bp and bn insn patterns with a zero_extend rtx inside them. From-SVN: r90898
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Nick Clifton
Nick Clifton
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e648d85ab2
commit
f99652b5e3
gcc
@ -1,3 +1,13 @@
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2004-11-19 Nick Clifton <nickc@redhat.com>
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* config/stormy16/stormy16.c (combine_bnp): Add code to handle
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zero_extension and lshiftrt insns.
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Replace uses of XEXP(...) with either SET_DEST() or SET_SRC()
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where appropriate.
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* config/stormy16.stormy16.md (bclrx3, bsetx3): New patterns
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to handle bp and bn insn patterns with a zero_extend rtx
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inside them.
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2004-11-19 Ian Lance Taylor <ian@wasabisystems.com>
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* config/arm/arm.md (generic_sched): Make const.
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@ -2570,9 +2570,12 @@ xstormy16_expand_builtin(tree exp, rtx target,
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static void
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combine_bnp (rtx insn)
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{
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int insn_code, regno, need_extend, mask;
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int insn_code, regno, need_extend;
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unsigned int mask;
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rtx cond, reg, and, load, qireg, mem;
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enum machine_mode load_mode = QImode;
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enum machine_mode and_mode = QImode;
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rtx shift = NULL_RTX;
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insn_code = recog_memoized (insn);
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if (insn_code != CODE_FOR_cbranchhi
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@ -2613,15 +2616,14 @@ combine_bnp (rtx insn)
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for (and = prev_real_insn (insn); and; and = prev_real_insn (and))
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{
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int and_code = recog_memoized (and);
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if (and_code == CODE_FOR_extendqihi2
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&& rtx_equal_p (XEXP (PATTERN (and), 0), reg)
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&& rtx_equal_p (XEXP (XEXP (PATTERN (and), 1), 0), qireg))
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{
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break;
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}
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&& rtx_equal_p (SET_DEST (PATTERN (and)), reg)
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&& rtx_equal_p (XEXP (SET_SRC (PATTERN (and)), 0), qireg))
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break;
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if (and_code == CODE_FOR_movhi_internal
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&& rtx_equal_p (XEXP (PATTERN (and), 0), reg))
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&& rtx_equal_p (SET_DEST (PATTERN (and)), reg))
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{
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/* This is for testing bit 15. */
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and = insn;
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@ -2630,6 +2632,7 @@ combine_bnp (rtx insn)
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if (reg_mentioned_p (reg, and))
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return;
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if (GET_CODE (and) != NOTE
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&& GET_CODE (and) != INSN)
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return;
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@ -2641,44 +2644,84 @@ combine_bnp (rtx insn)
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for (and = prev_real_insn (insn); and; and = prev_real_insn (and))
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{
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if (recog_memoized (and) == CODE_FOR_andhi3
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&& rtx_equal_p (XEXP (PATTERN (and), 0), reg)
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&& rtx_equal_p (XEXP (XEXP (PATTERN (and), 1), 0), reg))
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{
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break;
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}
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&& rtx_equal_p (SET_DEST (PATTERN (and)), reg)
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&& rtx_equal_p (XEXP (SET_SRC (PATTERN (and)), 0), reg))
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break;
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if (reg_mentioned_p (reg, and))
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return;
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if (GET_CODE (and) != NOTE
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&& GET_CODE (and) != INSN)
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return;
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}
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if (and)
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{
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/* Some mis-optimisations by GCC can generate a RIGHT-SHIFT
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followed by an AND like this:
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(parallel [(set (reg:HI r7) (lshiftrt:HI (reg:HI r7) (const_int 3)))
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(clobber (reg:BI carry))]
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(set (reg:HI r7) (and:HI (reg:HI r7) (const_int 1)))
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Attempt to detect this here. */
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for (shift = prev_real_insn (and); shift; shift = prev_real_insn (shift))
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{
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if (recog_memoized (shift) == CODE_FOR_lshrhi3
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&& rtx_equal_p (SET_DEST (XVECEXP (PATTERN (shift), 0, 0)), reg)
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&& rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 0), reg))
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break;
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if (reg_mentioned_p (reg, shift)
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|| (GET_CODE (shift) != NOTE
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&& GET_CODE (shift) != INSN))
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{
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shift = NULL_RTX;
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break;
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}
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}
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}
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}
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if (!and)
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return;
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for (load = prev_real_insn (and); load; load = prev_real_insn (load))
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for (load = shift ? prev_real_insn (shift) : prev_real_insn (and);
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load;
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load = prev_real_insn (load))
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{
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int load_code = recog_memoized (load);
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if (load_code == CODE_FOR_movhi_internal
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&& rtx_equal_p (XEXP (PATTERN (load), 0), reg)
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&& xstormy16_below100_operand (XEXP (PATTERN (load), 1), HImode)
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&& ! MEM_VOLATILE_P (XEXP (PATTERN (load), 1)))
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&& rtx_equal_p (SET_DEST (PATTERN (load)), reg)
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&& xstormy16_below100_operand (SET_SRC (PATTERN (load)), HImode)
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&& ! MEM_VOLATILE_P (SET_SRC (PATTERN (load))))
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{
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load_mode = HImode;
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break;
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}
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if (load_code == CODE_FOR_movqi_internal
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&& rtx_equal_p (XEXP (PATTERN (load), 0), qireg)
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&& xstormy16_below100_operand (XEXP (PATTERN (load), 1), QImode))
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&& rtx_equal_p (SET_DEST (PATTERN (load)), qireg)
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&& xstormy16_below100_operand (SET_SRC (PATTERN (load)), QImode))
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{
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load_mode = QImode;
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break;
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}
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if (load_code == CODE_FOR_zero_extendqihi2
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&& rtx_equal_p (SET_DEST (PATTERN (load)), reg)
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&& xstormy16_below100_operand (XEXP (SET_SRC (PATTERN (load)), 0), QImode))
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{
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load_mode = QImode;
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and_mode = HImode;
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break;
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}
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if (reg_mentioned_p (reg, load))
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return;
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if (GET_CODE (load) != NOTE
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&& GET_CODE (load) != INSN)
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return;
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@ -2686,19 +2729,33 @@ combine_bnp (rtx insn)
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if (!load)
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return;
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if (!need_extend)
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mem = SET_SRC (PATTERN (load));
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if (need_extend)
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{
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if (!xstormy16_onebit_set_operand (XEXP (XEXP (PATTERN (and), 1), 1), load_mode))
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return;
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mask = (int) INTVAL (XEXP (XEXP (PATTERN (and), 1), 1));
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mask = (load_mode == HImode) ? 0x8000 : 0x80;
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/* If the mem includes a zero-extend operation and we are
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going to generate a sign-extend operation then move the
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mem inside the zero-extend. */
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if (GET_CODE (mem) == ZERO_EXTEND)
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mem = XEXP (mem, 0);
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}
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else
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mask = (load_mode == HImode) ? 0x8000 : 0x80;
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{
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if (!xstormy16_onebit_set_operand (XEXP (SET_SRC (PATTERN (and)), 1), load_mode))
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return;
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mask = (int) INTVAL (XEXP (SET_SRC (PATTERN (and)), 1));
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if (shift)
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mask <<= INTVAL (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 1));
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}
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mem = XEXP (PATTERN (load), 1);
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if (load_mode == HImode)
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{
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rtx addr = XEXP (mem, 0);
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if (! (mask & 0xff))
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{
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addr = plus_constant (addr, 1);
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@ -2710,11 +2767,16 @@ combine_bnp (rtx insn)
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if (need_extend)
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XEXP (cond, 0) = gen_rtx_SIGN_EXTEND (HImode, mem);
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else
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XEXP (cond, 0) = gen_rtx_AND (QImode, mem, GEN_INT (mask));
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XEXP (cond, 0) = gen_rtx_AND (and_mode, mem, GEN_INT (mask));
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INSN_CODE (insn) = -1;
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delete_insn (load);
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if (and != insn)
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delete_insn (and);
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if (shift != NULL_RTX)
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delete_insn (shift);
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}
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static void
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@ -1268,6 +1268,19 @@
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[(set_attr "length" "4")
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(set_attr "psw_operand" "nop")])
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(define_insn "*bclrx3"
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[(set (pc)
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(if_then_else (eq:HI (and:HI (zero_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
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(match_operand:HI 2 "immediate_operand" "i"))
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(clobber (match_operand:BI 3 "" "=y"))]
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""
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"bn %1,%B2,%l0"
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[(set_attr "length" "4")
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(set_attr "psw_operand" "nop")])
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(define_insn "*bclr7"
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[(set (pc)
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(if_then_else (xor:HI (lshiftrt:HI (subreg:HI
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@ -1320,6 +1333,19 @@
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[(set_attr "length" "4")
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(set_attr "psw_operand" "nop")])
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(define_insn "*bsetx3"
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[(set (pc)
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(if_then_else (ne:HI (and:HI (zero_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
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(match_operand:HI 2 "immediate_operand" "i"))
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(clobber (match_operand:BI 3 "" "=y"))]
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""
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"bp %1,%B2,%l0"
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[(set_attr "length" "4")
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(set_attr "psw_operand" "nop")])
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(define_insn "*bset7"
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[(set (pc)
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(if_then_else (lshiftrt:HI (subreg:HI (match_operand:QI 1 "xstormy16_below100_operand" "W") 0)
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