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sparc.c (sparc_override_options): If not TARGET_FPU, turn off TARGET_VIS.
* config/sparc/sparc.c (sparc_override_options): If not TARGET_FPU, turn off TARGET_VIS. * config/sparc/sparc.h (TARGET_SWITCHES): Add no-vis. (LEGITIMATE_CONSTANT_P): Allow SF/DF mode zero when TARGET_VIS. * config/sparc/sparc.md (movsi_insn): Use fzeros not fzero. (movdi_insn_sp64): Add VIS fzero alternative. (clear_sf, clear_df): New VIS patterns. (movsf, movdf expanders): Allow fp_zero_operand flat out when TARGET_VIS. (one_cmpldi2_sp64): Provide new fnot1 VIS alternative. From-SVN: r21996
This commit is contained in:
Jakub Jelinek
David S. Miller
parent
04069e5c0c
commit
f952a23816
@ -1,3 +1,16 @@
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Wed Aug 26 05:09:27 1998 Jakub Jelinek <jj@sunsite.ms.mff.cuni.cz>
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* config/sparc/sparc.c (sparc_override_options): If not
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TARGET_FPU, turn off TARGET_VIS.
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* config/sparc/sparc.h (TARGET_SWITCHES): Add no-vis.
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(LEGITIMATE_CONSTANT_P): Allow SF/DF mode zero when TARGET_VIS.
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* config/sparc/sparc.md (movsi_insn): Use fzeros not fzero.
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(movdi_insn_sp64): Add VIS fzero alternative.
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(clear_sf, clear_df): New VIS patterns.
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(movsf, movdf expanders): Allow fp_zero_operand flat out when
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TARGET_VIS.
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(one_cmpldi2_sp64): Provide new fnot1 VIS alternative.
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Tue Aug 25 10:57:41 1998 Mark Mitchell <mark@markmitchell.com>
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* loop.c (n_times_set, n_times_used, may_not_optimize,
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@ -287,6 +287,10 @@ sparc_override_options ()
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/* Don't use stack biasing in 32 bit mode. */
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if (TARGET_ARCH32)
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target_flags &= ~MASK_STACK_BIAS;
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/* Don't allow -mvis if FPU is disabled. */
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if (! TARGET_FPU)
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target_flags &= ~MASK_VIS;
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/* Validate -malign-loops= value, or provide default. */
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if (sparc_align_loops_string)
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@ -501,6 +501,7 @@ extern int target_flags;
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{"v8plus", MASK_V8PLUS}, \
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{"no-v8plus", -MASK_V8PLUS}, \
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{"vis", MASK_VIS}, \
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{"no-vis", -MASK_VIS}, \
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/* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
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{"cypress", 0}, \
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{"sparclite", 0}, \
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@ -2266,10 +2267,13 @@ extern struct rtx_def *sparc_builtin_saveregs ();
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#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
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/* Nonzero if the constant value X is a legitimate general operand.
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Anything can be made to work except floating point constants. */
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Anything can be made to work except floating point constants.
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If TARGET_VIS, 0.0 can be made to work as well. */
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#define LEGITIMATE_CONSTANT_P(X) \
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(GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
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#define LEGITIMATE_CONSTANT_P(X) \
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(GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
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(TARGET_VIS && (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode) && \
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fp_zero_operand (X)))
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/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
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and check its validity for a certain class.
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@ -2152,7 +2152,7 @@
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ld\\t%1, %0
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st\\t%r1, %0
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st\\t%1, %0
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fzero\\t%0"
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fzeros\\t%0"
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[(set_attr "type" "move,fpmove,move,move,load,fpload,store,fpstore,fpmove")
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(set_attr "length" "1")])
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@ -2369,8 +2369,8 @@
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(set_attr "length" "1")])
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(define_insn "*movdi_insn_sp64"
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[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m")
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(match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e"))]
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[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m,b")
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(match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e,J"))]
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"TARGET_ARCH64 &&
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(register_operand (operands[0], DImode)
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|| reg_or_0_operand (operands[1], DImode))"
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@ -2382,8 +2382,9 @@
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stx\\t%r1, %0
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fmovd\\t%1, %0
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ldd\\t%1, %0
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std\\t%1, %0"
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[(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore")
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std\\t%1, %0
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fzero\\t%0"
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[(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore,fpmove")
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(set_attr "length" "1")])
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;; ??? revisit this...
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@ -2731,6 +2732,17 @@
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;; Floating point move insns
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(define_insn "*clear_sf"
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[(set (match_operand:SF 0 "general_operand" "=f")
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(match_operand:SF 1 "" ""))]
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"TARGET_VIS
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& GET_CODE (operands[0]) == REG
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&& fp_zero_operand (operands[1])"
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"fzeros\\t%0"
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[(set_attr "type" "fpmove")
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(set_attr "length" "1")])
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(define_insn "*movsf_const_intreg"
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[(set (match_operand:SF 0 "general_operand" "=f,r")
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(match_operand:SF 1 "" "m,F"))]
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@ -2809,6 +2821,11 @@
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if (GET_CODE (operands[0]) == REG
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&& CONSTANT_P (operands[1]))
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{
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if (TARGET_VIS
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& fp_zero_operand (operands[1]))
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goto movsf_is_ok;
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/* emit_group_store will send such bogosity to us when it is
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not storing directly into memory. So fix this up to avoid
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crashes in output_constant_pool. */
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@ -2885,10 +2902,37 @@
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[(set_attr "type" "move,load,store")
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(set_attr "length" "1")])
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(define_insn "*movdf_const_intreg"
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(define_insn "*clear_df"
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[(set (match_operand:DF 0 "general_operand" "=e")
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(match_operand:DF 1 "" ""))]
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"TARGET_VIS
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& GET_CODE (operands[0]) == REG
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&& fp_zero_operand (operands[1])"
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"fzero\\t%0"
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[(set_attr "type" "fpmove")
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(set_attr "length" "1")])
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(define_insn "*movdf_const_intreg_sp32"
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[(set (match_operand:DF 0 "general_operand" "=e,e,r")
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(match_operand:DF 1 "" "T,o,F"))]
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"TARGET_FPU
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"TARGET_FPU && ! TARGET_ARCH64
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& GET_CODE (operands[0]) == REG"
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"*
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{
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if (which_alternative == 0)
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return \"ldd\\t%1, %0\";
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else
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return \"#\";
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}"
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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(define_insn "*movdf_const_intreg_sp64"
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[(set (match_operand:DF 0 "general_operand" "=e,e,r")
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(match_operand:DF 1 "" "m,o,F"))]
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"TARGET_FPU && TARGET_ARCH64
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& GET_CODE (operands[0]) == REG"
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"*
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@ -2951,6 +2995,11 @@
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if (GET_CODE (operands[0]) == REG
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&& CONSTANT_P (operands[1]))
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{
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if (TARGET_VIS
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& fp_zero_operand (operands[1]))
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goto movdf_is_ok;
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/* emit_group_store will send such bogosity to us when it is
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not storing directly into memory. So fix this up to avoid
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crashes in output_constant_pool. */
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@ -6321,11 +6370,13 @@
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operands[5] = gen_lowpart (SImode, operands[1]);")
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(define_insn "*one_cmpldi2_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(not:DI (match_operand:DI 1 "arith_double_operand" "rHI")))]
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[(set (match_operand:DI 0 "register_operand" "=r,b")
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(not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))]
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"TARGET_ARCH64"
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"xnor\\t%%g0, %1, %0"
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[(set_attr "type" "unary")
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"@
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xnor\\t%%g0, %1, %0
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fnot1\\t%1, %0"
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[(set_attr "type" "unary,fp")
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(set_attr "length" "1")])
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(define_expand "one_cmplsi2"
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