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[ARM][GCC][5/2x]: MVE intrinsics with binary operands.

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This patch supports following MVE ACLE intrinsics with binary operands.

vqmovntq_u16, vqmovnbq_u16, vmulltq_poly_p8, vmullbq_poly_p8, vmovntq_u16, vmovnbq_u16, vmlaldavxq_u16, vmlaldavq_u16, vqmovuntq_s16, vqmovunbq_s16, vshlltq_n_u8, vshllbq_n_u8, vorrq_n_u16, vbicq_n_u16, vcmpneq_n_f16, vcmpneq_f16, vcmpltq_n_f16, vcmpltq_f16, vcmpleq_n_f16, vcmpleq_f16, vcmpgtq_n_f16, vcmpgtq_f16, vcmpgeq_n_f16, vcmpgeq_f16, vcmpeqq_n_f16, vcmpeqq_f16, vsubq_f16, vqmovntq_s16, vqmovnbq_s16, vqdmulltq_s16, vqdmulltq_n_s16, vqdmullbq_s16, vqdmullbq_n_s16, vorrq_f16, vornq_f16, vmulq_n_f16, vmulq_f16, vmovntq_s16, vmovnbq_s16, vmlsldavxq_s16, vmlsldavq_s16, vmlaldavxq_s16, vmlaldavq_s16, vminnmvq_f16, vminnmq_f16, vminnmavq_f16, vminnmaq_f16, vmaxnmvq_f16, vmaxnmq_f16, vmaxnmavq_f16, vmaxnmaq_f16, veorq_f16, vcmulq_rot90_f16, vcmulq_rot270_f16, vcmulq_rot180_f16, vcmulq_f16, vcaddq_rot90_f16, vcaddq_rot270_f16, vbicq_f16, vandq_f16, vaddq_n_f16, vabdq_f16, vshlltq_n_s8, vshllbq_n_s8, vorrq_n_s16, vbicq_n_s16, vqmovntq_u32, vqmovnbq_u32, vmulltq_poly_p16, vmullbq_poly_p16, vmovntq_u32, vmovnbq_u32, vmlaldavxq_u32, vmlaldavq_u32, vqmovuntq_s32, vqmovunbq_s32, vshlltq_n_u16, vshllbq_n_u16, vorrq_n_u32, vbicq_n_u32, vcmpneq_n_f32, vcmpneq_f32, vcmpltq_n_f32, vcmpltq_f32, vcmpleq_n_f32, vcmpleq_f32, vcmpgtq_n_f32, vcmpgtq_f32, vcmpgeq_n_f32, vcmpgeq_f32, vcmpeqq_n_f32, vcmpeqq_f32, vsubq_f32, vqmovntq_s32, vqmovnbq_s32, vqdmulltq_s32, vqdmulltq_n_s32, vqdmullbq_s32, vqdmullbq_n_s32, vorrq_f32, vornq_f32, vmulq_n_f32, vmulq_f32, vmovntq_s32, vmovnbq_s32, vmlsldavxq_s32, vmlsldavq_s32, vmlaldavxq_s32, vmlaldavq_s32, vminnmvq_f32, vminnmq_f32, vminnmavq_f32, vminnmaq_f32, vmaxnmvq_f32, vmaxnmq_f32, vmaxnmavq_f32, vmaxnmaq_f32, veorq_f32, vcmulq_rot90_f32, vcmulq_rot270_f32, vcmulq_rot180_f32, vcmulq_f32, vcaddq_rot90_f32, vcaddq_rot270_f32, vbicq_f32, vandq_f32, vaddq_n_f32, vabdq_f32, vshlltq_n_s16, vshllbq_n_s16, vorrq_n_s32, vbicq_n_s32, vrmlaldavhq_u32, vctp8q_m, vctp64q_m, vctp32q_m, vctp16q_m, vaddlvaq_u32, vrmlsldavhxq_s32, vrmlsldavhq_s32, vrmlaldavhxq_s32, vrmlaldavhq_s32, vcvttq_f16_f32, vcvtbq_f16_f32, vaddlvaq_s32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

The above intrinsics are defined using the already defined builtin qualifiers BINOP_NONE_NONE_IMM, BINOP_NONE_NONE_NONE, BINOP_UNONE_NONE_NONE, BINOP_UNONE_UNONE_IMM, BINOP_UNONE_UNONE_NONE, BINOP_UNONE_UNONE_UNONE.

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vqmovntq_u16): Define macro.
	(vqmovnbq_u16): Likewise.
	(vmulltq_poly_p8): Likewise.
	(vmullbq_poly_p8): Likewise.
	(vmovntq_u16): Likewise.
	(vmovnbq_u16): Likewise.
	(vmlaldavxq_u16): Likewise.
	(vmlaldavq_u16): Likewise.
	(vqmovuntq_s16): Likewise.
	(vqmovunbq_s16): Likewise.
	(vshlltq_n_u8): Likewise.
	(vshllbq_n_u8): Likewise.
	(vorrq_n_u16): Likewise.
	(vbicq_n_u16): Likewise.
	(vcmpneq_n_f16): Likewise.
	(vcmpneq_f16): Likewise.
	(vcmpltq_n_f16): Likewise.
	(vcmpltq_f16): Likewise.
	(vcmpleq_n_f16): Likewise.
	(vcmpleq_f16): Likewise.
	(vcmpgtq_n_f16): Likewise.
	(vcmpgtq_f16): Likewise.
	(vcmpgeq_n_f16): Likewise.
	(vcmpgeq_f16): Likewise.
	(vcmpeqq_n_f16): Likewise.
	(vcmpeqq_f16): Likewise.
	(vsubq_f16): Likewise.
	(vqmovntq_s16): Likewise.
	(vqmovnbq_s16): Likewise.
	(vqdmulltq_s16): Likewise.
	(vqdmulltq_n_s16): Likewise.
	(vqdmullbq_s16): Likewise.
	(vqdmullbq_n_s16): Likewise.
	(vorrq_f16): Likewise.
	(vornq_f16): Likewise.
	(vmulq_n_f16): Likewise.
	(vmulq_f16): Likewise.
	(vmovntq_s16): Likewise.
	(vmovnbq_s16): Likewise.
	(vmlsldavxq_s16): Likewise.
	(vmlsldavq_s16): Likewise.
	(vmlaldavxq_s16): Likewise.
	(vmlaldavq_s16): Likewise.
	(vminnmvq_f16): Likewise.
	(vminnmq_f16): Likewise.
	(vminnmavq_f16): Likewise.
	(vminnmaq_f16): Likewise.
	(vmaxnmvq_f16): Likewise.
	(vmaxnmq_f16): Likewise.
	(vmaxnmavq_f16): Likewise.
	(vmaxnmaq_f16): Likewise.
	(veorq_f16): Likewise.
	(vcmulq_rot90_f16): Likewise.
	(vcmulq_rot270_f16): Likewise.
	(vcmulq_rot180_f16): Likewise.
	(vcmulq_f16): Likewise.
	(vcaddq_rot90_f16): Likewise.
	(vcaddq_rot270_f16): Likewise.
	(vbicq_f16): Likewise.
	(vandq_f16): Likewise.
	(vaddq_n_f16): Likewise.
	(vabdq_f16): Likewise.
	(vshlltq_n_s8): Likewise.
	(vshllbq_n_s8): Likewise.
	(vorrq_n_s16): Likewise.
	(vbicq_n_s16): Likewise.
	(vqmovntq_u32): Likewise.
	(vqmovnbq_u32): Likewise.
	(vmulltq_poly_p16): Likewise.
	(vmullbq_poly_p16): Likewise.
	(vmovntq_u32): Likewise.
	(vmovnbq_u32): Likewise.
	(vmlaldavxq_u32): Likewise.
	(vmlaldavq_u32): Likewise.
	(vqmovuntq_s32): Likewise.
	(vqmovunbq_s32): Likewise.
	(vshlltq_n_u16): Likewise.
	(vshllbq_n_u16): Likewise.
	(vorrq_n_u32): Likewise.
	(vbicq_n_u32): Likewise.
	(vcmpneq_n_f32): Likewise.
	(vcmpneq_f32): Likewise.
	(vcmpltq_n_f32): Likewise.
	(vcmpltq_f32): Likewise.
	(vcmpleq_n_f32): Likewise.
	(vcmpleq_f32): Likewise.
	(vcmpgtq_n_f32): Likewise.
	(vcmpgtq_f32): Likewise.
	(vcmpgeq_n_f32): Likewise.
	(vcmpgeq_f32): Likewise.
	(vcmpeqq_n_f32): Likewise.
	(vcmpeqq_f32): Likewise.
	(vsubq_f32): Likewise.
	(vqmovntq_s32): Likewise.
	(vqmovnbq_s32): Likewise.
	(vqdmulltq_s32): Likewise.
	(vqdmulltq_n_s32): Likewise.
	(vqdmullbq_s32): Likewise.
	(vqdmullbq_n_s32): Likewise.
	(vorrq_f32): Likewise.
	(vornq_f32): Likewise.
	(vmulq_n_f32): Likewise.
	(vmulq_f32): Likewise.
	(vmovntq_s32): Likewise.
	(vmovnbq_s32): Likewise.
	(vmlsldavxq_s32): Likewise.
	(vmlsldavq_s32): Likewise.
	(vmlaldavxq_s32): Likewise.
	(vmlaldavq_s32): Likewise.
	(vminnmvq_f32): Likewise.
	(vminnmq_f32): Likewise.
	(vminnmavq_f32): Likewise.
	(vminnmaq_f32): Likewise.
	(vmaxnmvq_f32): Likewise.
	(vmaxnmq_f32): Likewise.
	(vmaxnmavq_f32): Likewise.
	(vmaxnmaq_f32): Likewise.
	(veorq_f32): Likewise.
	(vcmulq_rot90_f32): Likewise.
	(vcmulq_rot270_f32): Likewise.
	(vcmulq_rot180_f32): Likewise.
	(vcmulq_f32): Likewise.
	(vcaddq_rot90_f32): Likewise.
	(vcaddq_rot270_f32): Likewise.
	(vbicq_f32): Likewise.
	(vandq_f32): Likewise.
	(vaddq_n_f32): Likewise.
	(vabdq_f32): Likewise.
	(vshlltq_n_s16): Likewise.
	(vshllbq_n_s16): Likewise.
	(vorrq_n_s32): Likewise.
	(vbicq_n_s32): Likewise.
	(vrmlaldavhq_u32): Likewise.
	(vctp8q_m): Likewise.
	(vctp64q_m): Likewise.
	(vctp32q_m): Likewise.
	(vctp16q_m): Likewise.
	(vaddlvaq_u32): Likewise.
	(vrmlsldavhxq_s32): Likewise.
	(vrmlsldavhq_s32): Likewise.
	(vrmlaldavhxq_s32): Likewise.
	(vrmlaldavhq_s32): Likewise.
	(vcvttq_f16_f32): Likewise.
	(vcvtbq_f16_f32): Likewise.
	(vaddlvaq_s32): Likewise.
	(__arm_vqmovntq_u16): Define intrinsic.
	(__arm_vqmovnbq_u16): Likewise.
	(__arm_vmulltq_poly_p8): Likewise.
	(__arm_vmullbq_poly_p8): Likewise.
	(__arm_vmovntq_u16): Likewise.
	(__arm_vmovnbq_u16): Likewise.
	(__arm_vmlaldavxq_u16): Likewise.
	(__arm_vmlaldavq_u16): Likewise.
	(__arm_vqmovuntq_s16): Likewise.
	(__arm_vqmovunbq_s16): Likewise.
	(__arm_vshlltq_n_u8): Likewise.
	(__arm_vshllbq_n_u8): Likewise.
	(__arm_vorrq_n_u16): Likewise.
	(__arm_vbicq_n_u16): Likewise.
	(__arm_vcmpneq_n_f16): Likewise.
	(__arm_vcmpneq_f16): Likewise.
	(__arm_vcmpltq_n_f16): Likewise.
	(__arm_vcmpltq_f16): Likewise.
	(__arm_vcmpleq_n_f16): Likewise.
	(__arm_vcmpleq_f16): Likewise.
	(__arm_vcmpgtq_n_f16): Likewise.
	(__arm_vcmpgtq_f16): Likewise.
	(__arm_vcmpgeq_n_f16): Likewise.
	(__arm_vcmpgeq_f16): Likewise.
	(__arm_vcmpeqq_n_f16): Likewise.
	(__arm_vcmpeqq_f16): Likewise.
	(__arm_vsubq_f16): Likewise.
	(__arm_vqmovntq_s16): Likewise.
	(__arm_vqmovnbq_s16): Likewise.
	(__arm_vqdmulltq_s16): Likewise.
	(__arm_vqdmulltq_n_s16): Likewise.
	(__arm_vqdmullbq_s16): Likewise.
	(__arm_vqdmullbq_n_s16): Likewise.
	(__arm_vorrq_f16): Likewise.
	(__arm_vornq_f16): Likewise.
	(__arm_vmulq_n_f16): Likewise.
	(__arm_vmulq_f16): Likewise.
	(__arm_vmovntq_s16): Likewise.
	(__arm_vmovnbq_s16): Likewise.
	(__arm_vmlsldavxq_s16): Likewise.
	(__arm_vmlsldavq_s16): Likewise.
	(__arm_vmlaldavxq_s16): Likewise.
	(__arm_vmlaldavq_s16): Likewise.
	(__arm_vminnmvq_f16): Likewise.
	(__arm_vminnmq_f16): Likewise.
	(__arm_vminnmavq_f16): Likewise.
	(__arm_vminnmaq_f16): Likewise.
	(__arm_vmaxnmvq_f16): Likewise.
	(__arm_vmaxnmq_f16): Likewise.
	(__arm_vmaxnmavq_f16): Likewise.
	(__arm_vmaxnmaq_f16): Likewise.
	(__arm_veorq_f16): Likewise.
	(__arm_vcmulq_rot90_f16): Likewise.
	(__arm_vcmulq_rot270_f16): Likewise.
	(__arm_vcmulq_rot180_f16): Likewise.
	(__arm_vcmulq_f16): Likewise.
	(__arm_vcaddq_rot90_f16): Likewise.
	(__arm_vcaddq_rot270_f16): Likewise.
	(__arm_vbicq_f16): Likewise.
	(__arm_vandq_f16): Likewise.
	(__arm_vaddq_n_f16): Likewise.
	(__arm_vabdq_f16): Likewise.
	(__arm_vshlltq_n_s8): Likewise.
	(__arm_vshllbq_n_s8): Likewise.
	(__arm_vorrq_n_s16): Likewise.
	(__arm_vbicq_n_s16): Likewise.
	(__arm_vqmovntq_u32): Likewise.
	(__arm_vqmovnbq_u32): Likewise.
	(__arm_vmulltq_poly_p16): Likewise.
	(__arm_vmullbq_poly_p16): Likewise.
	(__arm_vmovntq_u32): Likewise.
	(__arm_vmovnbq_u32): Likewise.
	(__arm_vmlaldavxq_u32): Likewise.
	(__arm_vmlaldavq_u32): Likewise.
	(__arm_vqmovuntq_s32): Likewise.
	(__arm_vqmovunbq_s32): Likewise.
	(__arm_vshlltq_n_u16): Likewise.
	(__arm_vshllbq_n_u16): Likewise.
	(__arm_vorrq_n_u32): Likewise.
	(__arm_vbicq_n_u32): Likewise.
	(__arm_vcmpneq_n_f32): Likewise.
	(__arm_vcmpneq_f32): Likewise.
	(__arm_vcmpltq_n_f32): Likewise.
	(__arm_vcmpltq_f32): Likewise.
	(__arm_vcmpleq_n_f32): Likewise.
	(__arm_vcmpleq_f32): Likewise.
	(__arm_vcmpgtq_n_f32): Likewise.
	(__arm_vcmpgtq_f32): Likewise.
	(__arm_vcmpgeq_n_f32): Likewise.
	(__arm_vcmpgeq_f32): Likewise.
	(__arm_vcmpeqq_n_f32): Likewise.
	(__arm_vcmpeqq_f32): Likewise.
	(__arm_vsubq_f32): Likewise.
	(__arm_vqmovntq_s32): Likewise.
	(__arm_vqmovnbq_s32): Likewise.
	(__arm_vqdmulltq_s32): Likewise.
	(__arm_vqdmulltq_n_s32): Likewise.
	(__arm_vqdmullbq_s32): Likewise.
	(__arm_vqdmullbq_n_s32): Likewise.
	(__arm_vorrq_f32): Likewise.
	(__arm_vornq_f32): Likewise.
	(__arm_vmulq_n_f32): Likewise.
	(__arm_vmulq_f32): Likewise.
	(__arm_vmovntq_s32): Likewise.
	(__arm_vmovnbq_s32): Likewise.
	(__arm_vmlsldavxq_s32): Likewise.
	(__arm_vmlsldavq_s32): Likewise.
	(__arm_vmlaldavxq_s32): Likewise.
	(__arm_vmlaldavq_s32): Likewise.
	(__arm_vminnmvq_f32): Likewise.
	(__arm_vminnmq_f32): Likewise.
	(__arm_vminnmavq_f32): Likewise.
	(__arm_vminnmaq_f32): Likewise.
	(__arm_vmaxnmvq_f32): Likewise.
	(__arm_vmaxnmq_f32): Likewise.
	(__arm_vmaxnmavq_f32): Likewise.
	(__arm_vmaxnmaq_f32): Likewise.
	(__arm_veorq_f32): Likewise.
	(__arm_vcmulq_rot90_f32): Likewise.
	(__arm_vcmulq_rot270_f32): Likewise.
	(__arm_vcmulq_rot180_f32): Likewise.
	(__arm_vcmulq_f32): Likewise.
	(__arm_vcaddq_rot90_f32): Likewise.
	(__arm_vcaddq_rot270_f32): Likewise.
	(__arm_vbicq_f32): Likewise.
	(__arm_vandq_f32): Likewise.
	(__arm_vaddq_n_f32): Likewise.
	(__arm_vabdq_f32): Likewise.
	(__arm_vshlltq_n_s16): Likewise.
	(__arm_vshllbq_n_s16): Likewise.
	(__arm_vorrq_n_s32): Likewise.
	(__arm_vbicq_n_s32): Likewise.
	(__arm_vrmlaldavhq_u32): Likewise.
	(__arm_vctp8q_m): Likewise.
	(__arm_vctp64q_m): Likewise.
	(__arm_vctp32q_m): Likewise.
	(__arm_vctp16q_m): Likewise.
	(__arm_vaddlvaq_u32): Likewise.
	(__arm_vrmlsldavhxq_s32): Likewise.
	(__arm_vrmlsldavhq_s32): Likewise.
	(__arm_vrmlaldavhxq_s32): Likewise.
	(__arm_vrmlaldavhq_s32): Likewise.
	(__arm_vcvttq_f16_f32): Likewise.
	(__arm_vcvtbq_f16_f32): Likewise.
	(__arm_vaddlvaq_s32): Likewise.
	(vst4q): Define polymorphic variant.
	(vrndxq): Likewise.
	(vrndq): Likewise.
	(vrndpq): Likewise.
	(vrndnq): Likewise.
	(vrndmq): Likewise.
	(vrndaq): Likewise.
	(vrev64q): Likewise.
	(vnegq): Likewise.
	(vdupq_n): Likewise.
	(vabsq): Likewise.
	(vrev32q): Likewise.
	(vcvtbq_f32): Likewise.
	(vcvttq_f32): Likewise.
	(vcvtq): Likewise.
	(vsubq_n): Likewise.
	(vbrsrq_n): Likewise.
	(vcvtq_n): Likewise.
	(vsubq): Likewise.
	(vorrq): Likewise.
	(vabdq): Likewise.
	(vaddq_n): Likewise.
	(vandq): Likewise.
	(vbicq): Likewise.
	(vornq): Likewise.
	(vmulq_n): Likewise.
	(vmulq): Likewise.
	(vcaddq_rot270): Likewise.
	(vcmpeqq_n): Likewise.
	(vcmpeqq): Likewise.
	(vcaddq_rot90): Likewise.
	(vcmpgeq_n): Likewise.
	(vcmpgeq): Likewise.
	(vcmpgtq_n): Likewise.
	(vcmpgtq): Likewise.
	(vcmpgtq): Likewise.
	(vcmpleq_n): Likewise.
	(vcmpleq_n): Likewise.
	(vcmpleq): Likewise.
	(vcmpleq): Likewise.
	(vcmpltq_n): Likewise.
	(vcmpltq_n): Likewise.
	(vcmpltq): Likewise.
	(vcmpltq): Likewise.
	(vcmpneq_n): Likewise.
	(vcmpneq_n): Likewise.
	(vcmpneq): Likewise.
	(vcmpneq): Likewise.
	(vcmulq): Likewise.
	(vcmulq): Likewise.
	(vcmulq_rot180): Likewise.
	(vcmulq_rot180): Likewise.
	(vcmulq_rot270): Likewise.
	(vcmulq_rot270): Likewise.
	(vcmulq_rot90): Likewise.
	(vcmulq_rot90): Likewise.
	(veorq): Likewise.
	(veorq): Likewise.
	(vmaxnmaq): Likewise.
	(vmaxnmaq): Likewise.
	(vmaxnmavq): Likewise.
	(vmaxnmavq): Likewise.
	(vmaxnmq): Likewise.
	(vmaxnmq): Likewise.
	(vmaxnmvq): Likewise.
	(vmaxnmvq): Likewise.
	(vminnmaq): Likewise.
	(vminnmaq): Likewise.
	(vminnmavq): Likewise.
	(vminnmavq): Likewise.
	(vminnmq): Likewise.
	(vminnmq): Likewise.
	(vminnmvq): Likewise.
	(vminnmvq): Likewise.
	(vbicq_n): Likewise.
	(vqmovntq): Likewise.
	(vqmovntq): Likewise.
	(vqmovnbq): Likewise.
	(vqmovnbq): Likewise.
	(vmulltq_poly): Likewise.
	(vmulltq_poly): Likewise.
	(vmullbq_poly): Likewise.
	(vmullbq_poly): Likewise.
	(vmovntq): Likewise.
	(vmovntq): Likewise.
	(vmovnbq): Likewise.
	(vmovnbq): Likewise.
	(vmlaldavxq): Likewise.
	(vmlaldavxq): Likewise.
	(vqmovuntq): Likewise.
	(vqmovuntq): Likewise.
	(vshlltq_n): Likewise.
	(vshlltq_n): Likewise.
	(vshllbq_n): Likewise.
	(vshllbq_n): Likewise.
	(vorrq_n): Likewise.
	(vorrq_n): Likewise.
	(vmlaldavq): Likewise.
	(vmlaldavq): Likewise.
	(vqmovunbq): Likewise.
	(vqmovunbq): Likewise.
	(vqdmulltq_n): Likewise.
	(vqdmulltq_n): Likewise.
	(vqdmulltq): Likewise.
	(vqdmulltq): Likewise.
	(vqdmullbq_n): Likewise.
	(vqdmullbq_n): Likewise.
	(vqdmullbq): Likewise.
	(vqdmullbq): Likewise.
	(vaddlvaq): Likewise.
	(vaddlvaq): Likewise.
	(vrmlaldavhq): Likewise.
	(vrmlaldavhq): Likewise.
	(vrmlaldavhxq): Likewise.
	(vrmlaldavhxq): Likewise.
	(vrmlsldavhq): Likewise.
	(vrmlsldavhq): Likewise.
	(vrmlsldavhxq): Likewise.
	(vrmlsldavhxq): Likewise.
	(vmlsldavxq): Likewise.
	(vmlsldavxq): Likewise.
	(vmlsldavq): Likewise.
	(vmlsldavq): Likewise.
	* config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
	(BINOP_NONE_NONE_NONE): Likewise.
	(BINOP_UNONE_NONE_NONE): Likewise.
	(BINOP_UNONE_UNONE_IMM): Likewise.
	(BINOP_UNONE_UNONE_NONE): Likewise.
	(BINOP_UNONE_UNONE_UNONE): Likewise.
	* config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
	(mve_vaddlvaq_<supf>v4si): Likewise.
	(mve_vaddq_n_f<mode>): Likewise.
	(mve_vandq_f<mode>): Likewise.
	(mve_vbicq_f<mode>): Likewise.
	(mve_vbicq_n_<supf><mode>): Likewise.
	(mve_vcaddq_rot270_f<mode>): Likewise.
	(mve_vcaddq_rot90_f<mode>): Likewise.
	(mve_vcmpeqq_f<mode>): Likewise.
	(mve_vcmpeqq_n_f<mode>): Likewise.
	(mve_vcmpgeq_f<mode>): Likewise.
	(mve_vcmpgeq_n_f<mode>): Likewise.
	(mve_vcmpgtq_f<mode>): Likewise.
	(mve_vcmpgtq_n_f<mode>): Likewise.
	(mve_vcmpleq_f<mode>): Likewise.
	(mve_vcmpleq_n_f<mode>): Likewise.
	(mve_vcmpltq_f<mode>): Likewise.
	(mve_vcmpltq_n_f<mode>): Likewise.
	(mve_vcmpneq_f<mode>): Likewise.
	(mve_vcmpneq_n_f<mode>): Likewise.
	(mve_vcmulq_f<mode>): Likewise.
	(mve_vcmulq_rot180_f<mode>): Likewise.
	(mve_vcmulq_rot270_f<mode>): Likewise.
	(mve_vcmulq_rot90_f<mode>): Likewise.
	(mve_vctp<mode1>q_mhi): Likewise.
	(mve_vcvtbq_f16_f32v8hf): Likewise.
	(mve_vcvttq_f16_f32v8hf): Likewise.
	(mve_veorq_f<mode>): Likewise.
	(mve_vmaxnmaq_f<mode>): Likewise.
	(mve_vmaxnmavq_f<mode>): Likewise.
	(mve_vmaxnmq_f<mode>): Likewise.
	(mve_vmaxnmvq_f<mode>): Likewise.
	(mve_vminnmaq_f<mode>): Likewise.
	(mve_vminnmavq_f<mode>): Likewise.
	(mve_vminnmq_f<mode>): Likewise.
	(mve_vminnmvq_f<mode>): Likewise.
	(mve_vmlaldavq_<supf><mode>): Likewise.
	(mve_vmlaldavxq_<supf><mode>): Likewise.
	(mve_vmlsldavq_s<mode>): Likewise.
	(mve_vmlsldavxq_s<mode>): Likewise.
	(mve_vmovnbq_<supf><mode>): Likewise.
	(mve_vmovntq_<supf><mode>): Likewise.
	(mve_vmulq_f<mode>): Likewise.
	(mve_vmulq_n_f<mode>): Likewise.
	(mve_vornq_f<mode>): Likewise.
	(mve_vorrq_f<mode>): Likewise.
	(mve_vorrq_n_<supf><mode>): Likewise.
	(mve_vqdmullbq_n_s<mode>): Likewise.
	(mve_vqdmullbq_s<mode>): Likewise.
	(mve_vqdmulltq_n_s<mode>): Likewise.
	(mve_vqdmulltq_s<mode>): Likewise.
	(mve_vqmovnbq_<supf><mode>): Likewise.
	(mve_vqmovntq_<supf><mode>): Likewise.
	(mve_vqmovunbq_s<mode>): Likewise.
	(mve_vqmovuntq_s<mode>): Likewise.
	(mve_vrmlaldavhxq_sv4si): Likewise.
	(mve_vrmlsldavhq_sv4si): Likewise.
	(mve_vrmlsldavhxq_sv4si): Likewise.
	(mve_vshllbq_n_<supf><mode>): Likewise.
	(mve_vshlltq_n_<supf><mode>): Likewise.
	(mve_vsubq_f<mode>): Likewise.
	(mve_vmulltq_poly_p<mode>): Likewise.
	(mve_vmullbq_poly_p<mode>): Likewise.
	(mve_vrmlaldavhq_<supf>v4si): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabdq_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
This commit is contained in:
Srinath Parvathaneni 2020-03-17 15:44:52 +00:00 committed by Kyrylo Tkachov
parent 33203b4c27
commit f9355dee93
205 changed files with 7186 additions and 387 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

488
gcc/ChangeLog
View File

@ -1,3 +1,491 @@
2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vqmovntq_u16): Define macro.
(vqmovnbq_u16): Likewise.
(vmulltq_poly_p8): Likewise.
(vmullbq_poly_p8): Likewise.
(vmovntq_u16): Likewise.
(vmovnbq_u16): Likewise.
(vmlaldavxq_u16): Likewise.
(vmlaldavq_u16): Likewise.
(vqmovuntq_s16): Likewise.
(vqmovunbq_s16): Likewise.
(vshlltq_n_u8): Likewise.
(vshllbq_n_u8): Likewise.
(vorrq_n_u16): Likewise.
(vbicq_n_u16): Likewise.
(vcmpneq_n_f16): Likewise.
(vcmpneq_f16): Likewise.
(vcmpltq_n_f16): Likewise.
(vcmpltq_f16): Likewise.
(vcmpleq_n_f16): Likewise.
(vcmpleq_f16): Likewise.
(vcmpgtq_n_f16): Likewise.
(vcmpgtq_f16): Likewise.
(vcmpgeq_n_f16): Likewise.
(vcmpgeq_f16): Likewise.
(vcmpeqq_n_f16): Likewise.
(vcmpeqq_f16): Likewise.
(vsubq_f16): Likewise.
(vqmovntq_s16): Likewise.
(vqmovnbq_s16): Likewise.
(vqdmulltq_s16): Likewise.
(vqdmulltq_n_s16): Likewise.
(vqdmullbq_s16): Likewise.
(vqdmullbq_n_s16): Likewise.
(vorrq_f16): Likewise.
(vornq_f16): Likewise.
(vmulq_n_f16): Likewise.
(vmulq_f16): Likewise.
(vmovntq_s16): Likewise.
(vmovnbq_s16): Likewise.
(vmlsldavxq_s16): Likewise.
(vmlsldavq_s16): Likewise.
(vmlaldavxq_s16): Likewise.
(vmlaldavq_s16): Likewise.
(vminnmvq_f16): Likewise.
(vminnmq_f16): Likewise.
(vminnmavq_f16): Likewise.
(vminnmaq_f16): Likewise.
(vmaxnmvq_f16): Likewise.
(vmaxnmq_f16): Likewise.
(vmaxnmavq_f16): Likewise.
(vmaxnmaq_f16): Likewise.
(veorq_f16): Likewise.
(vcmulq_rot90_f16): Likewise.
(vcmulq_rot270_f16): Likewise.
(vcmulq_rot180_f16): Likewise.
(vcmulq_f16): Likewise.
(vcaddq_rot90_f16): Likewise.
(vcaddq_rot270_f16): Likewise.
(vbicq_f16): Likewise.
(vandq_f16): Likewise.
(vaddq_n_f16): Likewise.
(vabdq_f16): Likewise.
(vshlltq_n_s8): Likewise.
(vshllbq_n_s8): Likewise.
(vorrq_n_s16): Likewise.
(vbicq_n_s16): Likewise.
(vqmovntq_u32): Likewise.
(vqmovnbq_u32): Likewise.
(vmulltq_poly_p16): Likewise.
(vmullbq_poly_p16): Likewise.
(vmovntq_u32): Likewise.
(vmovnbq_u32): Likewise.
(vmlaldavxq_u32): Likewise.
(vmlaldavq_u32): Likewise.
(vqmovuntq_s32): Likewise.
(vqmovunbq_s32): Likewise.
(vshlltq_n_u16): Likewise.
(vshllbq_n_u16): Likewise.
(vorrq_n_u32): Likewise.
(vbicq_n_u32): Likewise.
(vcmpneq_n_f32): Likewise.
(vcmpneq_f32): Likewise.
(vcmpltq_n_f32): Likewise.
(vcmpltq_f32): Likewise.
(vcmpleq_n_f32): Likewise.
(vcmpleq_f32): Likewise.
(vcmpgtq_n_f32): Likewise.
(vcmpgtq_f32): Likewise.
(vcmpgeq_n_f32): Likewise.
(vcmpgeq_f32): Likewise.
(vcmpeqq_n_f32): Likewise.
(vcmpeqq_f32): Likewise.
(vsubq_f32): Likewise.
(vqmovntq_s32): Likewise.
(vqmovnbq_s32): Likewise.
(vqdmulltq_s32): Likewise.
(vqdmulltq_n_s32): Likewise.
(vqdmullbq_s32): Likewise.
(vqdmullbq_n_s32): Likewise.
(vorrq_f32): Likewise.
(vornq_f32): Likewise.
(vmulq_n_f32): Likewise.
(vmulq_f32): Likewise.
(vmovntq_s32): Likewise.
(vmovnbq_s32): Likewise.
(vmlsldavxq_s32): Likewise.
(vmlsldavq_s32): Likewise.
(vmlaldavxq_s32): Likewise.
(vmlaldavq_s32): Likewise.
(vminnmvq_f32): Likewise.
(vminnmq_f32): Likewise.
(vminnmavq_f32): Likewise.
(vminnmaq_f32): Likewise.
(vmaxnmvq_f32): Likewise.
(vmaxnmq_f32): Likewise.
(vmaxnmavq_f32): Likewise.
(vmaxnmaq_f32): Likewise.
(veorq_f32): Likewise.
(vcmulq_rot90_f32): Likewise.
(vcmulq_rot270_f32): Likewise.
(vcmulq_rot180_f32): Likewise.
(vcmulq_f32): Likewise.
(vcaddq_rot90_f32): Likewise.
(vcaddq_rot270_f32): Likewise.
(vbicq_f32): Likewise.
(vandq_f32): Likewise.
(vaddq_n_f32): Likewise.
(vabdq_f32): Likewise.
(vshlltq_n_s16): Likewise.
(vshllbq_n_s16): Likewise.
(vorrq_n_s32): Likewise.
(vbicq_n_s32): Likewise.
(vrmlaldavhq_u32): Likewise.
(vctp8q_m): Likewise.
(vctp64q_m): Likewise.
(vctp32q_m): Likewise.
(vctp16q_m): Likewise.
(vaddlvaq_u32): Likewise.
(vrmlsldavhxq_s32): Likewise.
(vrmlsldavhq_s32): Likewise.
(vrmlaldavhxq_s32): Likewise.
(vrmlaldavhq_s32): Likewise.
(vcvttq_f16_f32): Likewise.
(vcvtbq_f16_f32): Likewise.
(vaddlvaq_s32): Likewise.
(__arm_vqmovntq_u16): Define intrinsic.
(__arm_vqmovnbq_u16): Likewise.
(__arm_vmulltq_poly_p8): Likewise.
(__arm_vmullbq_poly_p8): Likewise.
(__arm_vmovntq_u16): Likewise.
(__arm_vmovnbq_u16): Likewise.
(__arm_vmlaldavxq_u16): Likewise.
(__arm_vmlaldavq_u16): Likewise.
(__arm_vqmovuntq_s16): Likewise.
(__arm_vqmovunbq_s16): Likewise.
(__arm_vshlltq_n_u8): Likewise.
(__arm_vshllbq_n_u8): Likewise.
(__arm_vorrq_n_u16): Likewise.
(__arm_vbicq_n_u16): Likewise.
(__arm_vcmpneq_n_f16): Likewise.
(__arm_vcmpneq_f16): Likewise.
(__arm_vcmpltq_n_f16): Likewise.
(__arm_vcmpltq_f16): Likewise.
(__arm_vcmpleq_n_f16): Likewise.
(__arm_vcmpleq_f16): Likewise.
(__arm_vcmpgtq_n_f16): Likewise.
(__arm_vcmpgtq_f16): Likewise.
(__arm_vcmpgeq_n_f16): Likewise.
(__arm_vcmpgeq_f16): Likewise.
(__arm_vcmpeqq_n_f16): Likewise.
(__arm_vcmpeqq_f16): Likewise.
(__arm_vsubq_f16): Likewise.
(__arm_vqmovntq_s16): Likewise.
(__arm_vqmovnbq_s16): Likewise.
(__arm_vqdmulltq_s16): Likewise.
(__arm_vqdmulltq_n_s16): Likewise.
(__arm_vqdmullbq_s16): Likewise.
(__arm_vqdmullbq_n_s16): Likewise.
(__arm_vorrq_f16): Likewise.
(__arm_vornq_f16): Likewise.
(__arm_vmulq_n_f16): Likewise.
(__arm_vmulq_f16): Likewise.
(__arm_vmovntq_s16): Likewise.
(__arm_vmovnbq_s16): Likewise.
(__arm_vmlsldavxq_s16): Likewise.
(__arm_vmlsldavq_s16): Likewise.
(__arm_vmlaldavxq_s16): Likewise.
(__arm_vmlaldavq_s16): Likewise.
(__arm_vminnmvq_f16): Likewise.
(__arm_vminnmq_f16): Likewise.
(__arm_vminnmavq_f16): Likewise.
(__arm_vminnmaq_f16): Likewise.
(__arm_vmaxnmvq_f16): Likewise.
(__arm_vmaxnmq_f16): Likewise.
(__arm_vmaxnmavq_f16): Likewise.
(__arm_vmaxnmaq_f16): Likewise.
(__arm_veorq_f16): Likewise.
(__arm_vcmulq_rot90_f16): Likewise.
(__arm_vcmulq_rot270_f16): Likewise.
(__arm_vcmulq_rot180_f16): Likewise.
(__arm_vcmulq_f16): Likewise.
(__arm_vcaddq_rot90_f16): Likewise.
(__arm_vcaddq_rot270_f16): Likewise.
(__arm_vbicq_f16): Likewise.
(__arm_vandq_f16): Likewise.
(__arm_vaddq_n_f16): Likewise.
(__arm_vabdq_f16): Likewise.
(__arm_vshlltq_n_s8): Likewise.
(__arm_vshllbq_n_s8): Likewise.
(__arm_vorrq_n_s16): Likewise.
(__arm_vbicq_n_s16): Likewise.
(__arm_vqmovntq_u32): Likewise.
(__arm_vqmovnbq_u32): Likewise.
(__arm_vmulltq_poly_p16): Likewise.
(__arm_vmullbq_poly_p16): Likewise.
(__arm_vmovntq_u32): Likewise.
(__arm_vmovnbq_u32): Likewise.
(__arm_vmlaldavxq_u32): Likewise.
(__arm_vmlaldavq_u32): Likewise.
(__arm_vqmovuntq_s32): Likewise.
(__arm_vqmovunbq_s32): Likewise.
(__arm_vshlltq_n_u16): Likewise.
(__arm_vshllbq_n_u16): Likewise.
(__arm_vorrq_n_u32): Likewise.
(__arm_vbicq_n_u32): Likewise.
(__arm_vcmpneq_n_f32): Likewise.
(__arm_vcmpneq_f32): Likewise.
(__arm_vcmpltq_n_f32): Likewise.
(__arm_vcmpltq_f32): Likewise.
(__arm_vcmpleq_n_f32): Likewise.
(__arm_vcmpleq_f32): Likewise.
(__arm_vcmpgtq_n_f32): Likewise.
(__arm_vcmpgtq_f32): Likewise.
(__arm_vcmpgeq_n_f32): Likewise.
(__arm_vcmpgeq_f32): Likewise.
(__arm_vcmpeqq_n_f32): Likewise.
(__arm_vcmpeqq_f32): Likewise.
(__arm_vsubq_f32): Likewise.
(__arm_vqmovntq_s32): Likewise.
(__arm_vqmovnbq_s32): Likewise.
(__arm_vqdmulltq_s32): Likewise.
(__arm_vqdmulltq_n_s32): Likewise.
(__arm_vqdmullbq_s32): Likewise.
(__arm_vqdmullbq_n_s32): Likewise.
(__arm_vorrq_f32): Likewise.
(__arm_vornq_f32): Likewise.
(__arm_vmulq_n_f32): Likewise.
(__arm_vmulq_f32): Likewise.
(__arm_vmovntq_s32): Likewise.
(__arm_vmovnbq_s32): Likewise.
(__arm_vmlsldavxq_s32): Likewise.
(__arm_vmlsldavq_s32): Likewise.
(__arm_vmlaldavxq_s32): Likewise.
(__arm_vmlaldavq_s32): Likewise.
(__arm_vminnmvq_f32): Likewise.
(__arm_vminnmq_f32): Likewise.
(__arm_vminnmavq_f32): Likewise.
(__arm_vminnmaq_f32): Likewise.
(__arm_vmaxnmvq_f32): Likewise.
(__arm_vmaxnmq_f32): Likewise.
(__arm_vmaxnmavq_f32): Likewise.
(__arm_vmaxnmaq_f32): Likewise.
(__arm_veorq_f32): Likewise.
(__arm_vcmulq_rot90_f32): Likewise.
(__arm_vcmulq_rot270_f32): Likewise.
(__arm_vcmulq_rot180_f32): Likewise.
(__arm_vcmulq_f32): Likewise.
(__arm_vcaddq_rot90_f32): Likewise.
(__arm_vcaddq_rot270_f32): Likewise.
(__arm_vbicq_f32): Likewise.
(__arm_vandq_f32): Likewise.
(__arm_vaddq_n_f32): Likewise.
(__arm_vabdq_f32): Likewise.
(__arm_vshlltq_n_s16): Likewise.
(__arm_vshllbq_n_s16): Likewise.
(__arm_vorrq_n_s32): Likewise.
(__arm_vbicq_n_s32): Likewise.
(__arm_vrmlaldavhq_u32): Likewise.
(__arm_vctp8q_m): Likewise.
(__arm_vctp64q_m): Likewise.
(__arm_vctp32q_m): Likewise.
(__arm_vctp16q_m): Likewise.
(__arm_vaddlvaq_u32): Likewise.
(__arm_vrmlsldavhxq_s32): Likewise.
(__arm_vrmlsldavhq_s32): Likewise.
(__arm_vrmlaldavhxq_s32): Likewise.
(__arm_vrmlaldavhq_s32): Likewise.
(__arm_vcvttq_f16_f32): Likewise.
(__arm_vcvtbq_f16_f32): Likewise.
(__arm_vaddlvaq_s32): Likewise.
(vst4q): Define polymorphic variant.
(vrndxq): Likewise.
(vrndq): Likewise.
(vrndpq): Likewise.
(vrndnq): Likewise.
(vrndmq): Likewise.
(vrndaq): Likewise.
(vrev64q): Likewise.
(vnegq): Likewise.
(vdupq_n): Likewise.
(vabsq): Likewise.
(vrev32q): Likewise.
(vcvtbq_f32): Likewise.
(vcvttq_f32): Likewise.
(vcvtq): Likewise.
(vsubq_n): Likewise.
(vbrsrq_n): Likewise.
(vcvtq_n): Likewise.
(vsubq): Likewise.
(vorrq): Likewise.
(vabdq): Likewise.
(vaddq_n): Likewise.
(vandq): Likewise.
(vbicq): Likewise.
(vornq): Likewise.
(vmulq_n): Likewise.
(vmulq): Likewise.
(vcaddq_rot270): Likewise.
(vcmpeqq_n): Likewise.
(vcmpeqq): Likewise.
(vcaddq_rot90): Likewise.
(vcmpgeq_n): Likewise.
(vcmpgeq): Likewise.
(vcmpgtq_n): Likewise.
(vcmpgtq): Likewise.
(vcmpgtq): Likewise.
(vcmpleq_n): Likewise.
(vcmpleq_n): Likewise.
(vcmpleq): Likewise.
(vcmpleq): Likewise.
(vcmpltq_n): Likewise.
(vcmpltq_n): Likewise.
(vcmpltq): Likewise.
(vcmpltq): Likewise.
(vcmpneq_n): Likewise.
(vcmpneq_n): Likewise.
(vcmpneq): Likewise.
(vcmpneq): Likewise.
(vcmulq): Likewise.
(vcmulq): Likewise.
(vcmulq_rot180): Likewise.
(vcmulq_rot180): Likewise.
(vcmulq_rot270): Likewise.
(vcmulq_rot270): Likewise.
(vcmulq_rot90): Likewise.
(vcmulq_rot90): Likewise.
(veorq): Likewise.
(veorq): Likewise.
(vmaxnmaq): Likewise.
(vmaxnmaq): Likewise.
(vmaxnmavq): Likewise.
(vmaxnmavq): Likewise.
(vmaxnmq): Likewise.
(vmaxnmq): Likewise.
(vmaxnmvq): Likewise.
(vmaxnmvq): Likewise.
(vminnmaq): Likewise.
(vminnmaq): Likewise.
(vminnmavq): Likewise.
(vminnmavq): Likewise.
(vminnmq): Likewise.
(vminnmq): Likewise.
(vminnmvq): Likewise.
(vminnmvq): Likewise.
(vbicq_n): Likewise.
(vqmovntq): Likewise.
(vqmovntq): Likewise.
(vqmovnbq): Likewise.
(vqmovnbq): Likewise.
(vmulltq_poly): Likewise.
(vmulltq_poly): Likewise.
(vmullbq_poly): Likewise.
(vmullbq_poly): Likewise.
(vmovntq): Likewise.
(vmovntq): Likewise.
(vmovnbq): Likewise.
(vmovnbq): Likewise.
(vmlaldavxq): Likewise.
(vmlaldavxq): Likewise.
(vqmovuntq): Likewise.
(vqmovuntq): Likewise.
(vshlltq_n): Likewise.
(vshlltq_n): Likewise.
(vshllbq_n): Likewise.
(vshllbq_n): Likewise.
(vorrq_n): Likewise.
(vorrq_n): Likewise.
(vmlaldavq): Likewise.
(vmlaldavq): Likewise.
(vqmovunbq): Likewise.
(vqmovunbq): Likewise.
(vqdmulltq_n): Likewise.
(vqdmulltq_n): Likewise.
(vqdmulltq): Likewise.
(vqdmulltq): Likewise.
(vqdmullbq_n): Likewise.
(vqdmullbq_n): Likewise.
(vqdmullbq): Likewise.
(vqdmullbq): Likewise.
(vaddlvaq): Likewise.
(vaddlvaq): Likewise.
(vrmlaldavhq): Likewise.
(vrmlaldavhq): Likewise.
(vrmlaldavhxq): Likewise.
(vrmlaldavhxq): Likewise.
(vrmlsldavhq): Likewise.
(vrmlsldavhq): Likewise.
(vrmlsldavhxq): Likewise.
(vrmlsldavhxq): Likewise.
(vmlsldavxq): Likewise.
(vmlsldavxq): Likewise.
(vmlsldavq): Likewise.
(vmlsldavq): Likewise.
* config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
(BINOP_NONE_NONE_NONE): Likewise.
(BINOP_UNONE_NONE_NONE): Likewise.
(BINOP_UNONE_UNONE_IMM): Likewise.
(BINOP_UNONE_UNONE_NONE): Likewise.
(BINOP_UNONE_UNONE_UNONE): Likewise.
* config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
(mve_vaddlvaq_<supf>v4si): Likewise.
(mve_vaddq_n_f<mode>): Likewise.
(mve_vandq_f<mode>): Likewise.
(mve_vbicq_f<mode>): Likewise.
(mve_vbicq_n_<supf><mode>): Likewise.
(mve_vcaddq_rot270_f<mode>): Likewise.
(mve_vcaddq_rot90_f<mode>): Likewise.
(mve_vcmpeqq_f<mode>): Likewise.
(mve_vcmpeqq_n_f<mode>): Likewise.
(mve_vcmpgeq_f<mode>): Likewise.
(mve_vcmpgeq_n_f<mode>): Likewise.
(mve_vcmpgtq_f<mode>): Likewise.
(mve_vcmpgtq_n_f<mode>): Likewise.
(mve_vcmpleq_f<mode>): Likewise.
(mve_vcmpleq_n_f<mode>): Likewise.
(mve_vcmpltq_f<mode>): Likewise.
(mve_vcmpltq_n_f<mode>): Likewise.
(mve_vcmpneq_f<mode>): Likewise.
(mve_vcmpneq_n_f<mode>): Likewise.
(mve_vcmulq_f<mode>): Likewise.
(mve_vcmulq_rot180_f<mode>): Likewise.
(mve_vcmulq_rot270_f<mode>): Likewise.
(mve_vcmulq_rot90_f<mode>): Likewise.
(mve_vctp<mode1>q_mhi): Likewise.
(mve_vcvtbq_f16_f32v8hf): Likewise.
(mve_vcvttq_f16_f32v8hf): Likewise.
(mve_veorq_f<mode>): Likewise.
(mve_vmaxnmaq_f<mode>): Likewise.
(mve_vmaxnmavq_f<mode>): Likewise.
(mve_vmaxnmq_f<mode>): Likewise.
(mve_vmaxnmvq_f<mode>): Likewise.
(mve_vminnmaq_f<mode>): Likewise.
(mve_vminnmavq_f<mode>): Likewise.
(mve_vminnmq_f<mode>): Likewise.
(mve_vminnmvq_f<mode>): Likewise.
(mve_vmlaldavq_<supf><mode>): Likewise.
(mve_vmlaldavxq_<supf><mode>): Likewise.
(mve_vmlsldavq_s<mode>): Likewise.
(mve_vmlsldavxq_s<mode>): Likewise.
(mve_vmovnbq_<supf><mode>): Likewise.
(mve_vmovntq_<supf><mode>): Likewise.
(mve_vmulq_f<mode>): Likewise.
(mve_vmulq_n_f<mode>): Likewise.
(mve_vornq_f<mode>): Likewise.
(mve_vorrq_f<mode>): Likewise.
(mve_vorrq_n_<supf><mode>): Likewise.
(mve_vqdmullbq_n_s<mode>): Likewise.
(mve_vqdmullbq_s<mode>): Likewise.
(mve_vqdmulltq_n_s<mode>): Likewise.
(mve_vqdmulltq_s<mode>): Likewise.
(mve_vqmovnbq_<supf><mode>): Likewise.
(mve_vqmovntq_<supf><mode>): Likewise.
(mve_vqmovunbq_s<mode>): Likewise.
(mve_vqmovuntq_s<mode>): Likewise.
(mve_vrmlaldavhxq_sv4si): Likewise.
(mve_vrmlsldavhq_sv4si): Likewise.
(mve_vrmlsldavhxq_sv4si): Likewise.
(mve_vshllbq_n_<supf><mode>): Likewise.
(mve_vshlltq_n_<supf><mode>): Likewise.
(mve_vsubq_f<mode>): Likewise.
(mve_vmulltq_poly_p<mode>): Likewise.
(mve_vmullbq_poly_p<mode>): Likewise.
(mve_vrmlaldavhq_<supf>v4si): Likewise.
2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>

2269
gcc/config/arm/arm_mve.h
View File

File diff suppressed because it is too large Load Diff

468
gcc/config/arm/arm_mve_builtins.def
View File

@ -18,198 +18,276 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf)
VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf)
VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf)
VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf)
VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf)
VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf)
VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf)
VAR3 (UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si)
VAR2 (UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi)
VAR2 (UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi)
VAR2 (UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi)
VAR2 (UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si)
VAR2 (UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si)
VAR2 (UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si)
VAR2 (UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si)
VAR2 (UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si)
VAR2 (UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si)
VAR1 (UNOP_SNONE_SNONE, vrev16q_s, v16qi)
VAR1 (UNOP_SNONE_SNONE, vaddlvq_s, v4si)
VAR3 (UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si)
VAR3 (UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si)
VAR3 (UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si)
VAR3 (UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si)
VAR3 (UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si)
VAR2 (UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi)
VAR2 (UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi)
VAR2 (UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi)
VAR2 (UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si)
VAR2 (UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si)
VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi)
VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si)
VAR1 (UNOP_UNONE_UNONE, vctp16q, hi)
VAR1 (UNOP_UNONE_UNONE, vctp32q, hi)
VAR1 (UNOP_UNONE_UNONE, vctp64q, hi)
VAR1 (UNOP_UNONE_UNONE, vctp8q, hi)
VAR1 (UNOP_UNONE_UNONE, vpnot, hi)
VAR2 (BINOP_NONE_NONE_NONE, vsubq_n_f, v8hf, v4sf)
VAR2 (BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf)
VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf)
VAR2 (BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf)
VAR2 (BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf)
VAR2 (BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si)
VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si)
VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di)
VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di)
VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si)
VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si)
VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vrmulhq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vrhaddq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vqsubq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vqsubq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vqaddq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vqaddq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vorrq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vornq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vmulq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vmulq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vmulltq_int_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vmullbq_int_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vmulhq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vmladavq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vminvq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vminq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vmaxvq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vmaxq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot90_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot270_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_r_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vrshlq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vrshlq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vqshlq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vqshlq_r_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vqrshlq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vqrshlq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vminavq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vminaq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vmaxavq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vmaxaq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vrshlq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vrshlq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vrmulhq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vrhaddq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqsubq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqsubq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqshlq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqshlq_r_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqrshlq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqrshlq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqrdmulhq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqrdmulhq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqdmulhq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqdmulhq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqaddq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vqaddq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vorrq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vornq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmulq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmulq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmulltq_int_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmullbq_int_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmulhq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmlsdavxq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmlsdavq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmladavxq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmladavq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vminvq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vminq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhaddq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, veorq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot90_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot270_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vbrsrq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vbicq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vandq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vaddvaq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vaddq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vabdq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_IMM, vshlq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_IMM, vrshrq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_IMM, vqshlq_n_s, v16qi, v8hi, v4si)
VAR5(STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vrndq_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vnegq_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf)
VAR2(UNOP_NONE_NONE, vabsq_f, v8hf, v4sf)
VAR1(UNOP_NONE_NONE, vrev32q_f, v8hf)
VAR1(UNOP_NONE_NONE, vcvttq_f32_f16, v4sf)
VAR1(UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf)
VAR2(UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf)
VAR2(UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf)
VAR3(UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si)
VAR3(UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si)
VAR2(UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi)
VAR2(UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi)
VAR2(UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi)
VAR2(UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si)
VAR2(UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si)
VAR2(UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si)
VAR2(UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si)
VAR2(UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si)
VAR2(UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si)
VAR1(UNOP_SNONE_SNONE, vrev16q_s, v16qi)
VAR1(UNOP_SNONE_SNONE, vaddlvq_s, v4si)
VAR3(UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si)
VAR3(UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si)
VAR3(UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si)
VAR3(UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si)
VAR3(UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si)
VAR2(UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi)
VAR2(UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi)
VAR2(UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi)
VAR2(UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si)
VAR2(UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si)
VAR2(UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si)
VAR2(UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si)
VAR2(UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si)
VAR2(UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si)
VAR1(UNOP_UNONE_UNONE, vrev16q_u, v16qi)
VAR1(UNOP_UNONE_UNONE, vaddlvq_u, v4si)
VAR1(UNOP_UNONE_UNONE, vctp16q, hi)
VAR1(UNOP_UNONE_UNONE, vctp32q, hi)
VAR1(UNOP_UNONE_UNONE, vctp64q, hi)
VAR1(UNOP_UNONE_UNONE, vctp8q, hi)
VAR1(UNOP_UNONE_UNONE, vpnot, hi)
VAR2(BINOP_NONE_NONE_NONE, vsubq_n_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf)
VAR2(BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf)
VAR2(BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si)
VAR2(BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si)
VAR4(BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di)
VAR4(BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di)
VAR3(BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si)
VAR1(BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si)
VAR1(BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vsubq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vrmulhq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vrhaddq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vqsubq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vqsubq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vqaddq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vqaddq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vorrq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vornq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vmulq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vmulq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vmulltq_int_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vmullbq_int_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vmulhq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vmladavq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vminvq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vminq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vmaxvq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vmaxq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vhsubq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcaddq_rot90_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vcaddq_rot270_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vshlq_r_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vrshlq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vrshlq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vqshlq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vqshlq_r_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vqrshlq_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vqrshlq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vminavq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vminaq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vmaxavq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vmaxaq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpneq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpltq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpltq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpleq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpleq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpgtq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpgtq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpgeq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpgeq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpeqq_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_NONE, vcmpeqq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vrshlq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vrshlq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vrmulhq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vrhaddq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqsubq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqsubq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqshlq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqshlq_r_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqrshlq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqrshlq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqrdmulhq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqrdmulhq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqdmulhq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqdmulhq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqaddq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vqaddq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vorrq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vornq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmulq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmulq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmulltq_int_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmullbq_int_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmulhq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmlsdavxq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmlsdavq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmladavxq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmladavq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vminvq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vminq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vhaddq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, veorq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vcaddq_rot90_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vcaddq_rot270_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vbrsrq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vbicq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vandq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vaddvaq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vaddq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_NONE, vabdq_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_IMM, vshlq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_IMM, vrshrq_n_s, v16qi, v8hi, v4si)
VAR3(BINOP_NONE_NONE_IMM, vqshlq_n_s, v16qi, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_UNONE, vqmovntq_u, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_UNONE, vqmovnbq_u, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_UNONE, vmulltq_poly_p, v16qi, v8hi)
VAR2(BINOP_UNONE_UNONE_UNONE, vmullbq_poly_p, v16qi, v8hi)
VAR2(BINOP_UNONE_UNONE_UNONE, vmovntq_u, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_UNONE, vmovnbq_u, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_UNONE, vmlaldavq_u, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_NONE, vqmovuntq_s, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_NONE, vqmovunbq_s, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi)
VAR2(BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi)
VAR2(BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si)
VAR2(BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si)
VAR2(BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpneq_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpltq_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpleq_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpgtq_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpgeq_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf)
VAR2(BINOP_UNONE_NONE_NONE, vcmpeqq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vqmovnbq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vqdmulltq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vqdmulltq_n_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vqdmullbq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vqdmullbq_n_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vorrq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vornq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vmulq_n_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vmulq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vmovntq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vmovnbq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vmlsldavxq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vmlsldavq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vmlaldavxq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vmlaldavq_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_NONE, vminnmvq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vminnmq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vminnmavq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vminnmaq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vmaxnmvq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vmaxnmq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vmaxnmavq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vmaxnmaq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, veorq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot90_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot270_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vcmulq_rot180_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vcmulq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vcaddq_rot90_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vcaddq_rot270_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vbicq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vandq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vaddq_n_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_NONE, vabdq_f, v8hf, v4sf)
VAR2(BINOP_NONE_NONE_IMM, vshlltq_n_s, v16qi, v8hi)
VAR2(BINOP_NONE_NONE_IMM, vshllbq_n_s, v16qi, v8hi)
VAR2(BINOP_NONE_NONE_IMM, vorrq_n_s, v8hi, v4si)
VAR2(BINOP_NONE_NONE_IMM, vbicq_n_s, v8hi, v4si)
VAR1(BINOP_UNONE_UNONE_UNONE, vrmlaldavhq_u, v4si)
VAR1(BINOP_UNONE_UNONE_UNONE, vctp8q_m, hi)
VAR1(BINOP_UNONE_UNONE_UNONE, vctp64q_m, hi)
VAR1(BINOP_UNONE_UNONE_UNONE, vctp32q_m, hi)
VAR1(BINOP_UNONE_UNONE_UNONE, vctp16q_m, hi)
VAR1(BINOP_UNONE_UNONE_UNONE, vaddlvaq_u, v4si)
VAR1(BINOP_NONE_NONE_NONE, vrmlsldavhxq_s, v4si)
VAR1(BINOP_NONE_NONE_NONE, vrmlsldavhq_s, v4si)
VAR1(BINOP_NONE_NONE_NONE, vrmlaldavhxq_s, v4si)
VAR1(BINOP_NONE_NONE_NONE, vrmlaldavhq_s, v4si)
VAR1(BINOP_NONE_NONE_NONE, vcvttq_f16_f32, v8hf)
VAR1(BINOP_NONE_NONE_NONE, vcvtbq_f16_f32, v8hf)
VAR1(BINOP_NONE_NONE_NONE, vaddlvaq_s, v4si)

1008
gcc/config/arm/mve.md
View File

File diff suppressed because it is too large Load Diff

150
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,153 @@
2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabdq_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vabdq_f16 (a, b);
}
/* { dg-final { scan-assembler "vabd.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vabdq (a, b);
}
/* { dg-final { scan-assembler "vabd.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vabdq_f32 (a, b);
}
/* { dg-final { scan-assembler "vabd.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vabdq (a, b);
}
/* { dg-final { scan-assembler "vabd.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int64_t a, int32x4_t b)
{
return vaddlvaq_s32 (a, b);
}
/* { dg-final { scan-assembler "vaddlva.s32" } } */
int64_t
foo1 (int64_t a, int32x4_t b)
{
return vaddlvaq (a, b);
}
/* { dg-final { scan-assembler "vaddlva.s32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint64_t
foo (uint64_t a, uint32x4_t b)
{
return vaddlvaq_u32 (a, b);
}
/* { dg-final { scan-assembler "vaddlva.u32" } } */
uint64_t
foo1 (uint64_t a, uint32x4_t b)
{
return vaddlvaq (a, b);
}
/* { dg-final { scan-assembler "vaddlva.u32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16_t b)
{
return vaddq_n_f16 (a, b);
}
/* { dg-final { scan-assembler "vadd.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16_t b)
{
return vaddq (a, b);
}
/* { dg-final { scan-assembler "vadd.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32_t b)
{
return vaddq_n_f32 (a, b);
}
/* { dg-final { scan-assembler "vadd.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32_t b)
{
return vaddq (a, b);
}
/* { dg-final { scan-assembler "vadd.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vandq_f16 (a, b);
}
/* { dg-final { scan-assembler "vand" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vandq (a, b);
}
/* { dg-final { scan-assembler "vand" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vandq_f32 (a, b);
}
/* { dg-final { scan-assembler "vand" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vandq (a, b);
}
/* { dg-final { scan-assembler "vand" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vbicq_f16 (a, b);
}
/* { dg-final { scan-assembler "vbic" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vbicq (a, b);
}
/* { dg-final { scan-assembler "vbic" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vbicq_f32 (a, b);
}
/* { dg-final { scan-assembler "vbic" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vbicq (a, b);
}
/* { dg-final { scan-assembler "vbic" } } */

14
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vbicq_n_s16 (a, 1);
}
/* { dg-final { scan-assembler "vbic.i16" } } */

14
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a)
{
return vbicq_n_s32 (a, 1);
}
/* { dg-final { scan-assembler "vbic.i32" } } */

14
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a)
{
return vbicq_n_u16 (a, 1);
}
/* { dg-final { scan-assembler "vbic.i16" } } */

14
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t a)
{
return vbicq_n_u32 (a, 1);
}
/* { dg-final { scan-assembler "vbic.i32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vcaddq_rot270_f16 (a, b);
}
/* { dg-final { scan-assembler "vcadd.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcaddq_rot270 (a, b);
}
/* { dg-final { scan-assembler "vcadd.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vcaddq_rot270_f32 (a, b);
}
/* { dg-final { scan-assembler "vcadd.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcaddq_rot270 (a, b);
}
/* { dg-final { scan-assembler "vcadd.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vcaddq_rot90_f16 (a, b);
}
/* { dg-final { scan-assembler "vcadd.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcaddq_rot90 (a, b);
}
/* { dg-final { scan-assembler "vcadd.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vcaddq_rot90_f32 (a, b);
}
/* { dg-final { scan-assembler "vcadd.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcaddq_rot90 (a, b);
}
/* { dg-final { scan-assembler "vcadd.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16x8_t b)
{
return vcmpeqq_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmpeqq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32x4_t b)
{
return vcmpeqq_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmpeqq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16_t b)
{
return vcmpeqq_n_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16_t b)
{
return vcmpeqq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32_t b)
{
return vcmpeqq_n_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32_t b)
{
return vcmpeqq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16x8_t b)
{
return vcmpgeq_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmpgeq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32x4_t b)
{
return vcmpgeq_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmpgeq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16_t b)
{
return vcmpgeq_n_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16_t b)
{
return vcmpgeq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32_t b)
{
return vcmpgeq_n_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32_t b)
{
return vcmpgeq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16x8_t b)
{
return vcmpgtq_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmpgtq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32x4_t b)
{
return vcmpgtq_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmpgtq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16_t b)
{
return vcmpgtq_n_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16_t b)
{
return vcmpgtq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32_t b)
{
return vcmpgtq_n_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32_t b)
{
return vcmpgtq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16x8_t b)
{
return vcmpleq_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmpleq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32x4_t b)
{
return vcmpleq_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmpleq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16_t b)
{
return vcmpleq_n_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16_t b)
{
return vcmpleq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32_t b)
{
return vcmpleq_n_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32_t b)
{
return vcmpleq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16x8_t b)
{
return vcmpltq_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmpltq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32x4_t b)
{
return vcmpltq_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmpltq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16_t b)
{
return vcmpltq_n_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16_t b)
{
return vcmpltq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32_t b)
{
return vcmpltq_n_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32_t b)
{
return vcmpltq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16x8_t b)
{
return vcmpneq_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmpneq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32x4_t b)
{
return vcmpneq_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmpneq (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16_t b)
{
return vcmpneq_n_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16_t b)
{
return vcmpneq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32_t b)
{
return vcmpneq_n_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32_t b)
{
return vcmpneq_n (a, b);
}
/* { dg-final { scan-assembler "vcmp.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vcmulq_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmulq (a, b);
}
/* { dg-final { scan-assembler "vcmul.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vcmulq_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmulq (a, b);
}
/* { dg-final { scan-assembler "vcmul.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vcmulq_rot180_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmulq_rot180 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vcmulq_rot180_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmulq_rot180 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vcmulq_rot270_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmulq_rot270 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vcmulq_rot270_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmulq_rot270 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vcmulq_rot90_f16 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vcmulq_rot90 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vcmulq_rot90_f32 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vcmulq_rot90 (a, b);
}
/* { dg-final { scan-assembler "vcmul.f32" } } */

23
gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c Normal file
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@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp16q_m (a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vctpt.16" } } */
mve_pred16_t
foo1 (uint32_t a, mve_pred16_t p)
{
return vctp16q_m (a, p);
}
/* { dg-final { scan-assembler "vpst" } } */

23
gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c Normal file
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@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp32q_m (a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vctpt.32" } } */
mve_pred16_t
foo1 (uint32_t a, mve_pred16_t p)
{
return vctp32q_m (a, p);
}
/* { dg-final { scan-assembler "vpst" } } */

23
gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c Normal file
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@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp64q_m (a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vctpt.64" } } */
mve_pred16_t
foo1 (uint32_t a, mve_pred16_t p)
{
return vctp64q_m (a, p);
}
/* { dg-final { scan-assembler "vpst" } } */

23
gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c Normal file
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@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp8q_m (a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vctpt.8" } } */
mve_pred16_t
foo1 (uint32_t a, mve_pred16_t p)
{
return vctp8q_m (a, p);
}
/* { dg-final { scan-assembler "vpst" } } */

14
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float32x4_t b)
{
return vcvtbq_f16_f32 (a, b);
}
/* { dg-final { scan-assembler "vcvtb.f16.f32" } } */

14
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float32x4_t b)
{
return vcvttq_f16_f32 (a, b);
}
/* { dg-final { scan-assembler "vcvtt.f16.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return veorq_f16 (a, b);
}
/* { dg-final { scan-assembler "veor" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return veorq (a, b);
}
/* { dg-final { scan-assembler "veor" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return veorq_f32 (a, b);
}
/* { dg-final { scan-assembler "veor" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return veorq (a, b);
}
/* { dg-final { scan-assembler "veor" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
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@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b)
int16x8_t
foo1 (int16x8_t a, int16_t b)
{
return vhaddq_n (a, b);
return vhaddq (a, b);
}
/* { dg-final { scan-assembler "vhadd.s16" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
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@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b)
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vhaddq_n (a, b);
return vhaddq (a, b);
}
/* { dg-final { scan-assembler "vhadd.s32" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
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@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b)
int8x16_t
foo1 (int8x16_t a, int8_t b)
{
return vhaddq_n (a, b);
return vhaddq (a, b);
}
/* { dg-final { scan-assembler "vhadd.s8" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
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@ -16,7 +16,7 @@ foo (uint16x8_t a, uint16_t b)
uint16x8_t
foo1 (uint16x8_t a, uint16_t b)
{
return vhaddq_n (a, b);
return vhaddq (a, b);
}
/* { dg-final { scan-assembler "vhadd.u16" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
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@ -16,7 +16,7 @@ foo (uint32x4_t a, uint32_t b)
uint32x4_t
foo1 (uint32x4_t a, uint32_t b)
{
return vhaddq_n (a, b);
return vhaddq (a, b);
}
/* { dg-final { scan-assembler "vhadd.u32" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
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@ -16,7 +16,7 @@ foo (uint8x16_t a, uint8_t b)
uint8x16_t
foo1 (uint8x16_t a, uint8_t b)
{
return vhaddq_n (a, b);
return vhaddq (a, b);
}
/* { dg-final { scan-assembler "vhadd.u8" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
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@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b)
int16x8_t
foo1 (int16x8_t a, int16_t b)
{
return vhsubq_n (a, b);
return vhsubq (a, b);
}
/* { dg-final { scan-assembler "vhsub.s16" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
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@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b)
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vhsubq_n (a, b);
return vhsubq (a, b);
}
/* { dg-final { scan-assembler "vhsub.s32" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
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@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b)
int8x16_t
foo1 (int8x16_t a, int8_t b)
{
return vhsubq_n (a, b);
return vhsubq (a, b);
}
/* { dg-final { scan-assembler "vhsub.s8" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
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@ -16,7 +16,7 @@ foo (uint16x8_t a, uint16_t b)
uint16x8_t
foo1 (uint16x8_t a, uint16_t b)
{
return vhsubq_n (a, b);
return vhsubq (a, b);
}
/* { dg-final { scan-assembler "vhsub.u16" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
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@ -16,7 +16,7 @@ foo (uint32x4_t a, uint32_t b)
uint32x4_t
foo1 (uint32x4_t a, uint32_t b)
{
return vhsubq_n (a, b);
return vhsubq (a, b);
}
/* { dg-final { scan-assembler "vhsub.u32" } } */

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
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@ -16,7 +16,7 @@ foo (uint8x16_t a, uint8_t b)
uint8x16_t
foo1 (uint8x16_t a, uint8_t b)
{
return vhsubq_n (a, b);
return vhsubq (a, b);
}
/* { dg-final { scan-assembler "vhsub.u8" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vmaxnmaq_f16 (a, b);
}
/* { dg-final { scan-assembler "vmaxnma.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vmaxnmaq (a, b);
}
/* { dg-final { scan-assembler "vmaxnma.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vmaxnmaq_f32 (a, b);
}
/* { dg-final { scan-assembler "vmaxnma.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vmaxnmaq (a, b);
}
/* { dg-final { scan-assembler "vmaxnma.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16_t
foo (float16_t a, float16x8_t b)
{
return vmaxnmavq_f16 (a, b);
}
/* { dg-final { scan-assembler "vmaxnmav.f16" } } */
float16_t
foo1 (float16_t a, float16x8_t b)
{
return vmaxnmavq (a, b);
}
/* { dg-final { scan-assembler "vmaxnmav.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32_t
foo (float32_t a, float32x4_t b)
{
return vmaxnmavq_f32 (a, b);
}
/* { dg-final { scan-assembler "vmaxnmav.f32" } } */
float32_t
foo1 (float32_t a, float32x4_t b)
{
return vmaxnmavq (a, b);
}
/* { dg-final { scan-assembler "vmaxnmav.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vmaxnmq_f16 (a, b);
}
/* { dg-final { scan-assembler "vmaxnm.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vmaxnmq (a, b);
}
/* { dg-final { scan-assembler "vmaxnm.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vmaxnmq_f32 (a, b);
}
/* { dg-final { scan-assembler "vmaxnm.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vmaxnmq (a, b);
}
/* { dg-final { scan-assembler "vmaxnm.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16_t
foo (float16_t a, float16x8_t b)
{
return vmaxnmvq_f16 (a, b);
}
/* { dg-final { scan-assembler "vmaxnmv.f16" } } */
float16_t
foo1 (float16_t a, float16x8_t b)
{
return vmaxnmvq (a, b);
}
/* { dg-final { scan-assembler "vmaxnmv.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32_t
foo (float32_t a, float32x4_t b)
{
return vmaxnmvq_f32 (a, b);
}
/* { dg-final { scan-assembler "vmaxnmv.f32" } } */
float32_t
foo1 (float32_t a, float32x4_t b)
{
return vmaxnmvq (a, b);
}
/* { dg-final { scan-assembler "vmaxnmv.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vminnmaq_f16 (a, b);
}
/* { dg-final { scan-assembler "vminnma.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vminnmaq (a, b);
}
/* { dg-final { scan-assembler "vminnma.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vminnmaq_f32 (a, b);
}
/* { dg-final { scan-assembler "vminnma.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vminnmaq (a, b);
}
/* { dg-final { scan-assembler "vminnma.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16_t
foo (float16_t a, float16x8_t b)
{
return vminnmavq_f16 (a, b);
}
/* { dg-final { scan-assembler "vminnmav.f16" } } */
float16_t
foo1 (float16_t a, float16x8_t b)
{
return vminnmavq (a, b);
}
/* { dg-final { scan-assembler "vminnmav.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32_t
foo (float32_t a, float32x4_t b)
{
return vminnmavq_f32 (a, b);
}
/* { dg-final { scan-assembler "vminnmav.f32" } } */
float32_t
foo1 (float32_t a, float32x4_t b)
{
return vminnmavq (a, b);
}
/* { dg-final { scan-assembler "vminnmav.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vminnmq_f16 (a, b);
}
/* { dg-final { scan-assembler "vminnm.f16" } } */
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vminnmq (a, b);
}
/* { dg-final { scan-assembler "vminnm.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vminnmq_f32 (a, b);
}
/* { dg-final { scan-assembler "vminnm.f32" } } */
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vminnmq (a, b);
}
/* { dg-final { scan-assembler "vminnm.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16_t
foo (float16_t a, float16x8_t b)
{
return vminnmvq_f16 (a, b);
}
/* { dg-final { scan-assembler "vminnmv.f16" } } */
float16_t
foo1 (float16_t a, float16x8_t b)
{
return vminnmvq (a, b);
}
/* { dg-final { scan-assembler "vminnmv.f16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32_t
foo (float32_t a, float32x4_t b)
{
return vminnmvq_f32 (a, b);
}
/* { dg-final { scan-assembler "vminnmv.f32" } } */
float32_t
foo1 (float32_t a, float32x4_t b)
{
return vminnmvq (a, b);
}
/* { dg-final { scan-assembler "vminnmv.f32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int16x8_t a, int16x8_t b)
{
return vmlaldavq_s16 (a, b);
}
/* { dg-final { scan-assembler "vmlaldav.s16" } } */
int64_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlaldavq (a, b);
}
/* { dg-final { scan-assembler "vmlaldav.s16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vmlaldavq_s32 (a, b);
}
/* { dg-final { scan-assembler "vmlaldav.s32" } } */
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlaldavq (a, b);
}
/* { dg-final { scan-assembler "vmlaldav.s32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint64_t
foo (uint16x8_t a, uint16x8_t b)
{
return vmlaldavq_u16 (a, b);
}
/* { dg-final { scan-assembler "vmlaldav.u16" } } */
uint64_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vmlaldavq (a, b);
}
/* { dg-final { scan-assembler "vmlaldav.u16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint64_t
foo (uint32x4_t a, uint32x4_t b)
{
return vmlaldavq_u32 (a, b);
}
/* { dg-final { scan-assembler "vmlaldav.u32" } } */
uint64_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vmlaldavq (a, b);
}
/* { dg-final { scan-assembler "vmlaldav.u32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int16x8_t a, int16x8_t b)
{
return vmlaldavxq_s16 (a, b);
}
/* { dg-final { scan-assembler "vmlaldavx.s16" } } */
int64_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlaldavxq (a, b);
}
/* { dg-final { scan-assembler "vmlaldavx.s16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vmlaldavxq_s32 (a, b);
}
/* { dg-final { scan-assembler "vmlaldavx.s32" } } */
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlaldavxq (a, b);
}
/* { dg-final { scan-assembler "vmlaldavx.s32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsldavq_s16 (a, b);
}
/* { dg-final { scan-assembler "vmlsldav.s16" } } */
int64_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsldavq (a, b);
}
/* { dg-final { scan-assembler "vmlsldav.s16" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsldavq_s32 (a, b);
}
/* { dg-final { scan-assembler "vmlsldav.s32" } } */
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsldavq (a, b);
}
/* { dg-final { scan-assembler "vmlsldav.s32" } } */

22
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c Normal file
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@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsldavxq_s16 (a, b);
}
/* { dg-final { scan-assembler "vmlsldavx.s16" } } */
int64_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsldavxq (a, b);
}
/* { dg-final { scan-assembler "vmlsldavx.s16" } } */

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