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[AArch64] Add support for SVE [SU]{MAX,MIN} immediate
This patch adds support for the immediate forms of SVE SMAX, SMIN, UMAX and UMIN. SMAX and SMIN take the same range as MUL, so the patch basically just moves and generalises the existing MUL patterns. 2019-08-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/constraints.md (vsb): New constraint. (vsm): Generalize description. * config/aarch64/iterators.md (SVE_INT_BINARY_IMM): New code iterator. (sve_imm_con): Handle smax, smin, umax and umin. (sve_imm_prefix): New code attribute. * config/aarch64/predicates.md (aarch64_sve_vsb_immediate) (aarch64_sve_vsb_operand): New predicates. (aarch64_sve_mul_immediate): Rename to... (aarch64_sve_vsm_immediate): ...this. (aarch64_sve_mul_operand): Rename to... (aarch64_sve_vsm_operand): ...this. * config/aarch64/aarch64-sve.md (mul<mode>3): Generalize to... (<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3): ...this. (*mul<mode>3, *post_ra_mul<mode>3): Generalize to... (*<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3) (*post_ra_<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3): ...these and add movprfx support for the immediate alternatives. (<su><maxmin><mode>3, *<su><maxmin><mode>3): Delete in favor of the above. (*<SVE_INT_BINARY_SD:optab><SVE_SDI:mode>3): Fix incorrect predicate for operand 3. gcc/testsuite/ * gcc.target/aarch64/sve/smax_1.c: New test. * gcc.target/aarch64/sve/smin_1.c: Likewise. * gcc.target/aarch64/sve/umax_1.c: Likewise. * gcc.target/aarch64/sve/umin_1.c: Likewise. From-SVN: r274439
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
e0a0be93d7
commit
f8c22a8bba
@ -1,3 +1,28 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/constraints.md (vsb): New constraint.
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(vsm): Generalize description.
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* config/aarch64/iterators.md (SVE_INT_BINARY_IMM): New code
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iterator.
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(sve_imm_con): Handle smax, smin, umax and umin.
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(sve_imm_prefix): New code attribute.
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* config/aarch64/predicates.md (aarch64_sve_vsb_immediate)
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(aarch64_sve_vsb_operand): New predicates.
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(aarch64_sve_mul_immediate): Rename to...
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(aarch64_sve_vsm_immediate): ...this.
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(aarch64_sve_mul_operand): Rename to...
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(aarch64_sve_vsm_operand): ...this.
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* config/aarch64/aarch64-sve.md (mul<mode>3): Generalize to...
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(<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3): ...this.
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(*mul<mode>3, *post_ra_mul<mode>3): Generalize to...
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(*<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3)
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(*post_ra_<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3): ...these and
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add movprfx support for the immediate alternatives.
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(<su><maxmin><mode>3, *<su><maxmin><mode>3): Delete in favor
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of the above.
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(*<SVE_INT_BINARY_SD:optab><SVE_SDI:mode>3): Fix incorrect predicate
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for operand 3.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/predicates.md (aarch64_simd_imm_one): New predicate.
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@ -64,13 +64,11 @@
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;; ---- [INT] Subtraction
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;; ---- [INT] Take address
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;; ---- [INT] Absolute difference
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;; ---- [INT] Multiplication
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;; ---- [INT] Highpart multiplication
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;; ---- [INT] Division
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;; ---- [INT] Binary logical operations
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;; ---- [INT] Binary logical operations (inverted second input)
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;; ---- [INT] Shifts
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;; ---- [INT] Maximum and minimum
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;; ---- [FP] General binary arithmetic corresponding to rtx codes
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;; ---- [FP] General binary arithmetic corresponding to unspecs
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;; ---- [FP] Addition
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@ -1622,19 +1620,77 @@
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;; -------------------------------------------------------------------------
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;; ---- [INT] General binary arithmetic corresponding to rtx codes
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;; -------------------------------------------------------------------------
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;; Includes merging patterns for:
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;; - ADD
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;; - AND
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;; - EOR
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;; Includes:
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;; - ADD (merging form only)
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;; - AND (merging form only)
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;; - EOR (merging form only)
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;; - MUL
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;; - ORR
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;; - ORR (merging form only)
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;; - SMAX
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;; - SMIN
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;; - SUB
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;; - SUB (merging form only)
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;; - UMAX
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;; - UMIN
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;; -------------------------------------------------------------------------
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;; Unpredicated integer binary operations that have an immediate form.
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(define_expand "<optab><mode>3"
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_I
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[(match_dup 3)
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(SVE_INT_BINARY_IMM:SVE_I
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(match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "aarch64_sve_<sve_imm_con>_operand"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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{
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operands[3] = aarch64_ptrue_reg (<VPRED>mode);
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}
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)
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;; Integer binary operations that have an immediate form, predicated
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;; with a PTRUE. We don't actually need the predicate for the first
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;; and third alternatives, but using Upa or X isn't likely to gain much
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;; and would make the instruction seem less uniform to the register
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;; allocator.
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(define_insn_and_split "*<optab><mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
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(SVE_INT_BINARY_IMM:SVE_I
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(match_operand:SVE_I 2 "register_operand" "%0, 0, w, w")
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(match_operand:SVE_I 3 "aarch64_sve_<sve_imm_con>_operand" "<sve_imm_con>, w, <sve_imm_con>, w"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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"@
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#
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<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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#
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movprfx\t%0, %2\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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; Split the unpredicated form after reload, so that we don't have
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; the unnecessary PTRUE.
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"&& reload_completed
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&& !register_operand (operands[3], <MODE>mode)"
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[(set (match_dup 0) (SVE_INT_BINARY_IMM:SVE_I (match_dup 2) (match_dup 3)))]
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""
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[(set_attr "movprfx" "*,*,yes,yes")]
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)
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;; Unpredicated binary operations with a constant (post-RA only).
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;; These are generated by splitting a predicated instruction whose
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;; predicate is unused.
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(define_insn "*post_ra_<optab><mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(SVE_INT_BINARY_IMM:SVE_I
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(match_operand:SVE_I 1 "register_operand" "0, w")
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(match_operand:SVE_I 2 "aarch64_sve_<sve_imm_con>_immediate")))]
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"TARGET_SVE && reload_completed"
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"@
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<sve_int_op>\t%0.<Vetype>, %0.<Vetype>, #%<sve_imm_prefix>2
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movprfx\t%0, %1\;<sve_int_op>\t%0.<Vetype>, %0.<Vetype>, #%<sve_imm_prefix>2"
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[(set_attr "movprfx" "*,yes")]
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)
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;; Predicated integer operations with merging.
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(define_expand "cond_<optab><mode>"
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[(set (match_operand:SVE_I 0 "register_operand")
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@ -1865,68 +1921,6 @@
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[(set_attr "movprfx" "*,yes")]
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Multiplication
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - MUL
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;; -------------------------------------------------------------------------
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;; Unpredicated multiplication.
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(define_expand "mul<mode>3"
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_I
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[(match_dup 3)
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(mult:SVE_I
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(match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "aarch64_sve_mul_operand"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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{
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operands[3] = aarch64_ptrue_reg (<VPRED>mode);
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}
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)
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;; Multiplication predicated with a PTRUE. We don't actually need the
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;; predicate for the first alternative, but using Upa or X isn't likely
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;; to gain much and would make the instruction seem less uniform to the
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;; register allocator.
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(define_insn_and_split "*mul<mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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(mult:SVE_I
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(match_operand:SVE_I 2 "register_operand" "%0, 0, w")
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(match_operand:SVE_I 3 "aarch64_sve_mul_operand" "vsm, w, w"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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"@
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#
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mul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0, %2\;mul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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; Split the unpredicated form after reload, so that we don't have
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; the unnecessary PTRUE.
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"&& reload_completed
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&& !register_operand (operands[3], <MODE>mode)"
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[(set (match_dup 0) (mult:SVE_I (match_dup 2) (match_dup 3)))]
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""
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[(set_attr "movprfx" "*,*,yes")]
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)
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;; Unpredicated multiplications by a constant (post-RA only).
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;; These are generated by splitting a predicated instruction whose
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;; predicate is unused.
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(define_insn "*post_ra_mul<mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w")
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(mult:SVE_I
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(match_operand:SVE_I 1 "register_operand" "0")
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(match_operand:SVE_I 2 "aarch64_sve_mul_immediate")))]
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"TARGET_SVE && reload_completed"
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"mul\t%0.<Vetype>, %0.<Vetype>, #%2"
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)
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;; Merging forms are handled through SVE_INT_BINARY.
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;; -------------------------------------------------------------------------
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;; ---- [INT] Highpart multiplication
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;; -------------------------------------------------------------------------
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@ -1998,7 +1992,7 @@
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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(SVE_INT_BINARY_SD:SVE_SDI
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(match_operand:SVE_SDI 2 "register_operand" "0, w, w")
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(match_operand:SVE_SDI 3 "aarch64_sve_mul_operand" "w, 0, w"))]
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(match_operand:SVE_SDI 3 "register_operand" "w, 0, w"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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"@
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@ -2218,47 +2212,6 @@
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"<shift>\t%0.<Vetype>, %1.<Vetype>, #%2"
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Maximum and minimum
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - SMAX
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;; - SMIN
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;; - UMAX
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;; - UMIN
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;; -------------------------------------------------------------------------
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;; Unpredicated integer MAX/MIN.
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(define_expand "<su><maxmin><mode>3"
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_I
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[(match_dup 3)
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(MAXMIN:SVE_I (match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "register_operand"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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{
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operands[3] = aarch64_ptrue_reg (<VPRED>mode);
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}
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)
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;; Integer MAX/MIN predicated with a PTRUE.
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(define_insn "*<su><maxmin><mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(MAXMIN:SVE_I (match_operand:SVE_I 2 "register_operand" "%0, w")
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(match_operand:SVE_I 3 "register_operand" "w, w"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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"@
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<su><maxmin>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0, %2\;<su><maxmin>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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[(set_attr "movprfx" "*,yes")]
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)
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;; Merging forms are handled through SVE_INT_BINARY.
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;; -------------------------------------------------------------------------
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;; ---- [FP] General binary arithmetic corresponding to rtx codes
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;; -------------------------------------------------------------------------
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@ -388,6 +388,12 @@
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arithmetic instructions."
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(match_operand 0 "aarch64_sve_arith_immediate"))
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(define_constraint "vsb"
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"@internal
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A constraint that matches an immediate operand valid for SVE UMAX
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and UMIN operations."
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(match_operand 0 "aarch64_sve_vsb_immediate"))
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(define_constraint "vsc"
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"@internal
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A constraint that matches a signed immediate operand valid for SVE
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@ -420,9 +426,9 @@
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(define_constraint "vsm"
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"@internal
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A constraint that matches an immediate operand valid for SVE MUL
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operations."
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(match_operand 0 "aarch64_sve_mul_immediate"))
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A constraint that matches an immediate operand valid for SVE MUL,
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SMAX and SMIN operations."
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(match_operand 0 "aarch64_sve_vsm_immediate"))
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(define_constraint "vsA"
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"@internal
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@ -1285,6 +1285,9 @@
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;; SVE integer binary division operations.
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(define_code_iterator SVE_INT_BINARY_SD [div udiv])
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;; SVE integer binary operations that have an immediate form.
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(define_code_iterator SVE_INT_BINARY_IMM [mult smax smin umax umin])
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;; SVE floating-point operations with an unpredicated all-register form.
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(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
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@ -1499,7 +1502,12 @@
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(mult "fmul")])
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;; The SVE immediate constraint to use for an rtl code.
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(define_code_attr sve_imm_con [(eq "vsc")
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(define_code_attr sve_imm_con [(mult "vsm")
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(smax "vsm")
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(smin "vsm")
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(umax "vsb")
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(umin "vsb")
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(eq "vsc")
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(ne "vsc")
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(lt "vsc")
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(ge "vsc")
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@ -1510,6 +1518,13 @@
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(geu "vsd")
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(gtu "vsd")])
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;; The prefix letter to use when printing an immediate operand.
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(define_code_attr sve_imm_prefix [(mult "")
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(smax "")
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(smin "")
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(umax "D")
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(umin "D")])
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;; -------------------------------------------------------------------
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;; Int Iterators.
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;; -------------------------------------------------------------------
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@ -615,7 +615,15 @@
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(and (match_code "const,const_vector")
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(match_test "aarch64_sve_bitmask_immediate_p (op)")))
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(define_predicate "aarch64_sve_mul_immediate"
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;; Used for SVE UMAX and UMIN.
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(define_predicate "aarch64_sve_vsb_immediate"
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(and (match_code "const_vector")
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(match_test "GET_MODE_INNER (GET_MODE (op)) == QImode
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? aarch64_const_vec_all_same_in_range_p (op, -128, 127)
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: aarch64_const_vec_all_same_in_range_p (op, 0, 255)")))
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;; Used for SVE MUL, SMAX and SMIN.
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(define_predicate "aarch64_sve_vsm_immediate"
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(and (match_code "const,const_vector")
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(match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)")))
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@ -668,9 +676,13 @@
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_simd_rshift_imm")))
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(define_predicate "aarch64_sve_mul_operand"
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(define_predicate "aarch64_sve_vsb_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_sve_mul_immediate")))
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(match_operand 0 "aarch64_sve_vsb_immediate")))
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(define_predicate "aarch64_sve_vsm_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_sve_vsm_immediate")))
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(define_predicate "aarch64_sve_cmp_vsc_operand"
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(ior (match_operand 0 "register_operand")
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@ -1,3 +1,10 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/smax_1.c: New test.
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* gcc.target/aarch64/sve/smin_1.c: Likewise.
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* gcc.target/aarch64/sve/umax_1.c: Likewise.
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* gcc.target/aarch64/sve/umin_1.c: Likewise.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/cnot_1.c: New test.
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71
gcc/testsuite/gcc.target/aarch64/sve/smax_1.c
Normal file
71
gcc/testsuite/gcc.target/aarch64/sve/smax_1.c
Normal file
@ -0,0 +1,71 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O3 --save-temps" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define DO_REGREG_OPS(TYPE) \
|
||||
void varith_##TYPE##_reg (TYPE *dst, TYPE *src, int count) \
|
||||
{ \
|
||||
for (int i = 0; i < count; ++i) \
|
||||
dst[i] = dst[i] > src[i] ? dst[i] : src[i]; \
|
||||
}
|
||||
|
||||
#define DO_IMMEDIATE_OPS(VALUE, TYPE, NAME) \
|
||||
void varithimm_##NAME##_##TYPE (TYPE *dst, int count) \
|
||||
{ \
|
||||
for (int i = 0; i < count; ++i) \
|
||||
dst[i] = dst[i] > (TYPE) VALUE ? dst[i] : (TYPE) VALUE; \
|
||||
}
|
||||
|
||||
#define DO_ARITH_OPS(TYPE) \
|
||||
DO_REGREG_OPS (TYPE); \
|
||||
DO_IMMEDIATE_OPS (0, TYPE, 0); \
|
||||
DO_IMMEDIATE_OPS (86, TYPE, 86); \
|
||||
DO_IMMEDIATE_OPS (109, TYPE, 109); \
|
||||
DO_IMMEDIATE_OPS (141, TYPE, 141); \
|
||||
DO_IMMEDIATE_OPS (-1, TYPE, minus1); \
|
||||
DO_IMMEDIATE_OPS (-110, TYPE, minus110); \
|
||||
DO_IMMEDIATE_OPS (-141, TYPE, minus141);
|
||||
|
||||
DO_ARITH_OPS (int8_t)
|
||||
DO_ARITH_OPS (int16_t)
|
||||
DO_ARITH_OPS (int32_t)
|
||||
DO_ARITH_OPS (int64_t)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #115\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #141\n} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-1\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-115\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-141\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #141\n} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #-1\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #-110\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #-141\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #141\n} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #-1\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #-110\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #-141\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.d, z[0-9]+\.d, #0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.d, z[0-9]+\.d, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.d, z[0-9]+\.d, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmax\tz[0-9]+\.d, z[0-9]+\.d, #141\n} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.d, z[0-9]+\.d, #-1\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.d, z[0-9]+\.d, #-110\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmax\tz[0-9]+\.d, z[0-9]+\.d, #-141\n} } } */
|
||||
71
gcc/testsuite/gcc.target/aarch64/sve/smin_1.c
Normal file
71
gcc/testsuite/gcc.target/aarch64/sve/smin_1.c
Normal file
@ -0,0 +1,71 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O3 --save-temps" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define DO_REGREG_OPS(TYPE) \
|
||||
void varith_##TYPE##_reg (TYPE *dst, TYPE *src, int count) \
|
||||
{ \
|
||||
for (int i = 0; i < count; ++i) \
|
||||
dst[i] = dst[i] < src[i] ? dst[i] : src[i]; \
|
||||
}
|
||||
|
||||
#define DO_IMMEDIATE_OPS(VALUE, TYPE, NAME) \
|
||||
void varithimm_##NAME##_##TYPE (TYPE *dst, int count) \
|
||||
{ \
|
||||
for (int i = 0; i < count; ++i) \
|
||||
dst[i] = dst[i] < (TYPE) VALUE ? dst[i] : (TYPE) VALUE; \
|
||||
}
|
||||
|
||||
#define DO_ARITH_OPS(TYPE) \
|
||||
DO_REGREG_OPS (TYPE); \
|
||||
DO_IMMEDIATE_OPS (0, TYPE, 0); \
|
||||
DO_IMMEDIATE_OPS (86, TYPE, 86); \
|
||||
DO_IMMEDIATE_OPS (109, TYPE, 109); \
|
||||
DO_IMMEDIATE_OPS (141, TYPE, 141); \
|
||||
DO_IMMEDIATE_OPS (-1, TYPE, minus1); \
|
||||
DO_IMMEDIATE_OPS (-110, TYPE, minus110); \
|
||||
DO_IMMEDIATE_OPS (-141, TYPE, minus141);
|
||||
|
||||
DO_ARITH_OPS (int8_t)
|
||||
DO_ARITH_OPS (int16_t)
|
||||
DO_ARITH_OPS (int32_t)
|
||||
DO_ARITH_OPS (int64_t)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #115\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #141\n} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-1\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-115\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-141\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #141\n} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #-1\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #-110\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #-141\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #141\n} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #-1\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #-110\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #-141\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.d, z[0-9]+\.d, #0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.d, z[0-9]+\.d, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.d, z[0-9]+\.d, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmin\tz[0-9]+\.d, z[0-9]+\.d, #141\n} } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.d, z[0-9]+\.d, #-1\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.d, z[0-9]+\.d, #-110\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsmin\tz[0-9]+\.d, z[0-9]+\.d, #-141\n} } } */
|
||||
65
gcc/testsuite/gcc.target/aarch64/sve/umax_1.c
Normal file
65
gcc/testsuite/gcc.target/aarch64/sve/umax_1.c
Normal file
@ -0,0 +1,65 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O3 --save-temps" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define DO_REGREG_OPS(TYPE) \
|
||||
void varith_##TYPE##_reg (TYPE *dst, TYPE *src, int count) \
|
||||
{ \
|
||||
for (int i = 0; i < count; ++i) \
|
||||
dst[i] = dst[i] > src[i] ? dst[i] : src[i]; \
|
||||
}
|
||||
|
||||
#define DO_IMMEDIATE_OPS(VALUE, TYPE) \
|
||||
void varithimm_##VALUE##_##TYPE (TYPE *dst, int count) \
|
||||
{ \
|
||||
for (int i = 0; i < count; ++i) \
|
||||
dst[i] = dst[i] > (TYPE) VALUE ? dst[i] : (TYPE) VALUE; \
|
||||
}
|
||||
|
||||
#define DO_ARITH_OPS(TYPE) \
|
||||
DO_REGREG_OPS (TYPE); \
|
||||
DO_IMMEDIATE_OPS (2, TYPE); \
|
||||
DO_IMMEDIATE_OPS (86, TYPE); \
|
||||
DO_IMMEDIATE_OPS (109, TYPE); \
|
||||
DO_IMMEDIATE_OPS (141, TYPE); \
|
||||
DO_IMMEDIATE_OPS (229, TYPE); \
|
||||
DO_IMMEDIATE_OPS (255, TYPE); \
|
||||
DO_IMMEDIATE_OPS (256, TYPE);
|
||||
|
||||
DO_ARITH_OPS (uint8_t)
|
||||
DO_ARITH_OPS (uint16_t)
|
||||
DO_ARITH_OPS (uint32_t)
|
||||
DO_ARITH_OPS (uint64_t)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #141\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #229\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #255\n} } } */
|
||||
/* { dg-final { scan-assembler-not {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #256\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #141\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #229\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #255\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #256\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #141\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #229\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #255\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #256\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.d, z[0-9]+\.d, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.d, z[0-9]+\.d, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.d, z[0-9]+\.d, #141\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.d, z[0-9]+\.d, #229\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.d, z[0-9]+\.d, #255\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tumax\tz[0-9]+\.d, z[0-9]+\.d, #256\n} } } */
|
||||
65
gcc/testsuite/gcc.target/aarch64/sve/umin_1.c
Normal file
65
gcc/testsuite/gcc.target/aarch64/sve/umin_1.c
Normal file
@ -0,0 +1,65 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O3 --save-temps" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define DO_REGREG_OPS(TYPE) \
|
||||
void varith_##TYPE##_reg (TYPE *dst, TYPE *src, int count) \
|
||||
{ \
|
||||
for (int i = 0; i < count; ++i) \
|
||||
dst[i] = dst[i] < src[i] ? dst[i] : src[i]; \
|
||||
}
|
||||
|
||||
#define DO_IMMEDIATE_OPS(VALUE, TYPE) \
|
||||
void varithimm_##VALUE##_##TYPE (TYPE *dst, int count) \
|
||||
{ \
|
||||
for (int i = 0; i < count; ++i) \
|
||||
dst[i] = dst[i] < (TYPE) VALUE ? dst[i] : (TYPE) VALUE; \
|
||||
}
|
||||
|
||||
#define DO_ARITH_OPS(TYPE) \
|
||||
DO_REGREG_OPS (TYPE); \
|
||||
DO_IMMEDIATE_OPS (2, TYPE); \
|
||||
DO_IMMEDIATE_OPS (86, TYPE); \
|
||||
DO_IMMEDIATE_OPS (109, TYPE); \
|
||||
DO_IMMEDIATE_OPS (141, TYPE); \
|
||||
DO_IMMEDIATE_OPS (229, TYPE); \
|
||||
DO_IMMEDIATE_OPS (255, TYPE); \
|
||||
DO_IMMEDIATE_OPS (256, TYPE);
|
||||
|
||||
DO_ARITH_OPS (uint8_t)
|
||||
DO_ARITH_OPS (uint16_t)
|
||||
DO_ARITH_OPS (uint32_t)
|
||||
DO_ARITH_OPS (uint64_t)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #141\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #229\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #255\n} } } */
|
||||
/* { dg-final { scan-assembler-not {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #256\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #141\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #229\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #255\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #256\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #141\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #229\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #255\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #256\n} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.d, z[0-9]+\.d, #86\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.d, z[0-9]+\.d, #109\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.d, z[0-9]+\.d, #141\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.d, z[0-9]+\.d, #229\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.d, z[0-9]+\.d, #255\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tumin\tz[0-9]+\.d, z[0-9]+\.d, #256\n} } } */
|
||||
Loading…
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Reference in New Issue
Block a user