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doc: normalize 3DNow! spelling and spacing.

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gcc/:
	* doc/extend.texi (Vector Extensions, X86 Built-in Functions):
	Use '3DNow!' for the extension of that name, ensure normal space
	after the string.
	* doc/invoke.texi (i386 and x86-64 Options): Likewise.

From-SVN: r157215
This commit is contained in:
Ralf Wildenhues 2010-03-04 03:01:21 +00:00 committed by Ralf Wildenhues
parent 0f752f4435
commit f8723eb6ec
3 changed files with 17 additions and 10 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2010-03-04 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* doc/extend.texi (Vector Extensions, X86 Built-in Functions):
Use '3DNow!' for the extension of that name, ensure normal space
after the string.
* doc/invoke.texi (i386 and x86-64 Options): Likewise.
2010-03-03 Jeff Law <law@redhat.com>
* PR middle-end/32693

4
gcc/doc/extend.texi
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@ -6056,7 +6056,7 @@ purposes.
On some targets, the instruction set contains SIMD vector instructions that
operate on multiple values contained in one large register at the same time.
For example, on the i386 the MMX, 3Dnow! and SSE extensions can be used
For example, on the i386 the MMX, 3DNow!@: and SSE extensions can be used
this way.
The first step in using these extensions is to provide the necessary data
@ -8201,7 +8201,7 @@ The following machine modes are available for use with MMX built-in functions
vector of eight 8-bit integers. Some of the built-in functions operate on
MMX registers as a whole 64-bit entity, these use @code{V1DI} as their mode.
If 3Dnow extensions are enabled, @code{V2SF} is used as a mode for a vector
If 3DNow!@: extensions are enabled, @code{V2SF} is used as a mode for a vector
of two 32-bit floating point values.
If SSE extensions are enabled, @code{V4SF} is used for a vector of four 32-bit

16
gcc/doc/invoke.texi
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@ -11715,36 +11715,36 @@ instruction set support.
@item k6
AMD K6 CPU with MMX instruction set support.
@item k6-2, k6-3
Improved versions of AMD K6 CPU with MMX and 3dNOW!@: instruction set support.
Improved versions of AMD K6 CPU with MMX and 3DNow!@: instruction set support.
@item athlon, athlon-tbird
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and SSE prefetch instructions
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow!@: and SSE prefetch instructions
support.
@item athlon-4, athlon-xp, athlon-mp
Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and full SSE
Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow!@: and full SSE
instruction set support.
@item k8, opteron, athlon64, athlon-fx
AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW!@: and 64-bit instruction set extensions.)
MMX, SSE, SSE2, 3DNow!, enhanced 3DNow!@: and 64-bit instruction set extensions.)
@item k8-sse3, opteron-sse3, athlon64-sse3
Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
@item amdfam10, barcelona
AMD Family 10h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit
supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
instruction set extensions.)
@item winchip-c6
IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.
@item winchip2
IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!@:
IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3DNow!@:
instruction set support.
@item c3
Via C3 CPU with MMX and 3dNOW!@: instruction set support. (No scheduling is
Via C3 CPU with MMX and 3DNow!@: instruction set support. (No scheduling is
implemented for this chip.)
@item c3-2
Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
implemented for this chip.)
@item geode
Embedded AMD CPU with MMX and 3dNOW! instruction set support.
Embedded AMD CPU with MMX and 3DNow!@: instruction set support.
@end table
While picking a specific @var{cpu-type} will schedule things appropriately