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[AArch64] Add gather loads for partial SVE modes
This patch adds support for gather loads of partial vectors, where the vector base or offset elements can be wider than the elements being loaded. 2019-11-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (SVE_24, SVE_2, SVE_4): New mode iterators. * config/aarch64/aarch64-sve.md (gather_load<SVE_FULL_SD:mode><v_int_equiv>): Extend to... (gather_load<SVE_24:mode><v_int_container>): ...this. (mask_gather_load<SVE_FULL_S:mode><v_int_equiv>): Extend to... (mask_gather_load<SVE_4:mode><v_int_container>): ...this. (mask_gather_load<SVE_FULL_D:mode><v_int_equiv>): Extend to... (mask_gather_load<SVE_2:mode><v_int_container>): ...this. (*mask_gather_load<SVE_2:mode><v_int_container>_<su>xtw_unpacked): New pattern. (*mask_gather_load<SVE_FULL_D:mode><v_int_equiv>_sxtw): Extend to... (*mask_gather_load<SVE_2:mode><v_int_equiv>_sxtw): ...this. Allow the nominal extension predicate to be different from the load predicate. (*mask_gather_load<SVE_FULL_D:mode><v_int_equiv>_uxtw): Extend to... (*mask_gather_load<SVE_2:mode><v_int_equiv>_uxtw): ...this. gcc/testsuite/ * gcc.target/aarch64/sve/gather_load_1.c (TEST_LOOP): Start at 0. (TEST_ALL): Add tests for 8-bit and 16-bit elements. * gcc.target/aarch64/sve/gather_load_2.c: Update accordingly. * gcc.target/aarch64/sve/gather_load_3.c (TEST_LOOP): Start at 0. (TEST_ALL): Add tests for 8-bit and 16-bit elements. * gcc.target/aarch64/sve/gather_load_4.c: Update accordingly. * gcc.target/aarch64/sve/gather_load_5.c (TEST_LOOP): Start at 0. (TEST_ALL): Add tests for 8-bit, 16-bit and 32-bit elements. * gcc.target/aarch64/sve/gather_load_6.c: Add --param aarch64-sve-compare-costs=0. (TEST_LOOP): Start at 0. * gcc.target/aarch64/sve/gather_load_7.c: Add --param aarch64-sve-compare-costs=0. * gcc.target/aarch64/sve/gather_load_8.c: New test. * gcc.target/aarch64/sve/gather_load_9.c: Likewise. * gcc.target/aarch64/sve/mask_gather_load_6.c: Add --param aarch64-sve-compare-costs=0. From-SVN: r278345
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
2d56600c8d
commit
f8186eeaf3
@ -1,3 +1,23 @@
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/iterators.md (SVE_24, SVE_2, SVE_4): New mode
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iterators.
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* config/aarch64/aarch64-sve.md
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(gather_load<SVE_FULL_SD:mode><v_int_equiv>): Extend to...
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(gather_load<SVE_24:mode><v_int_container>): ...this.
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(mask_gather_load<SVE_FULL_S:mode><v_int_equiv>): Extend to...
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(mask_gather_load<SVE_4:mode><v_int_container>): ...this.
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(mask_gather_load<SVE_FULL_D:mode><v_int_equiv>): Extend to...
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(mask_gather_load<SVE_2:mode><v_int_container>): ...this.
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(*mask_gather_load<SVE_2:mode><v_int_container>_<su>xtw_unpacked):
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New pattern.
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(*mask_gather_load<SVE_FULL_D:mode><v_int_equiv>_sxtw): Extend to...
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(*mask_gather_load<SVE_2:mode><v_int_equiv>_sxtw): ...this.
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Allow the nominal extension predicate to be different from the
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load predicate.
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(*mask_gather_load<SVE_FULL_D:mode><v_int_equiv>_uxtw): Extend to...
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(*mask_gather_load<SVE_2:mode><v_int_equiv>_uxtw): ...this.
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-sve.md
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@ -1302,12 +1302,12 @@
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;; -------------------------------------------------------------------------
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;; Unpredicated gather loads.
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(define_expand "gather_load<mode><v_int_equiv>"
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[(set (match_operand:SVE_FULL_SD 0 "register_operand")
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(unspec:SVE_FULL_SD
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(define_expand "gather_load<mode><v_int_container>"
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[(set (match_operand:SVE_24 0 "register_operand")
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(unspec:SVE_24
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[(match_dup 5)
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(match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>")
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(match_operand:<V_INT_EQUIV> 2 "register_operand")
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(match_operand:<V_INT_CONTAINER> 2 "register_operand")
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(match_operand:DI 3 "const_int_operand")
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(match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>")
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(mem:BLK (scratch))]
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@ -1320,85 +1320,116 @@
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;; Predicated gather loads for 32-bit elements. Operand 3 is true for
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;; unsigned extension and false for signed extension.
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(define_insn "mask_gather_load<mode><v_int_equiv>"
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[(set (match_operand:SVE_FULL_S 0 "register_operand" "=w, w, w, w, w, w")
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(unspec:SVE_FULL_S
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(define_insn "mask_gather_load<mode><v_int_container>"
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[(set (match_operand:SVE_4 0 "register_operand" "=w, w, w, w, w, w")
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(unspec:SVE_4
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[(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
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(match_operand:DI 1 "aarch64_sve_gather_offset_w" "Z, vgw, rk, rk, rk, rk")
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(match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>" "Z, vgw, rk, rk, rk, rk")
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(match_operand:VNx4SI 2 "register_operand" "w, w, w, w, w, w")
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(match_operand:DI 3 "const_int_operand" "Ui1, Ui1, Z, Ui1, Z, Ui1")
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(match_operand:DI 4 "aarch64_gather_scale_operand_w" "Ui1, Ui1, Ui1, Ui1, i, i")
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(match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, Ui1, i, i")
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(mem:BLK (scratch))]
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UNSPEC_LD1_GATHER))]
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"TARGET_SVE"
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"@
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ld1w\t%0.s, %5/z, [%2.s]
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ld1w\t%0.s, %5/z, [%2.s, #%1]
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ld1w\t%0.s, %5/z, [%1, %2.s, sxtw]
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ld1w\t%0.s, %5/z, [%1, %2.s, uxtw]
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ld1w\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
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ld1w\t%0.s, %5/z, [%1, %2.s, uxtw %p4]"
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ld1<Vesize>\t%0.s, %5/z, [%2.s]
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ld1<Vesize>\t%0.s, %5/z, [%2.s, #%1]
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ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
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ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
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ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
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ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]"
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)
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;; Predicated gather loads for 64-bit elements. The value of operand 3
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;; doesn't matter in this case.
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(define_insn "mask_gather_load<mode><v_int_equiv>"
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[(set (match_operand:SVE_FULL_D 0 "register_operand" "=w, w, w, w")
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(unspec:SVE_FULL_D
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(define_insn "mask_gather_load<mode><v_int_container>"
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[(set (match_operand:SVE_2 0 "register_operand" "=w, w, w, w")
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(unspec:SVE_2
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[(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
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(match_operand:DI 1 "aarch64_sve_gather_offset_d" "Z, vgd, rk, rk")
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(match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>" "Z, vgd, rk, rk")
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(match_operand:VNx2DI 2 "register_operand" "w, w, w, w")
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(match_operand:DI 3 "const_int_operand")
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(match_operand:DI 4 "aarch64_gather_scale_operand_d" "Ui1, Ui1, Ui1, i")
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(match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, i")
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(mem:BLK (scratch))]
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UNSPEC_LD1_GATHER))]
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"TARGET_SVE"
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"@
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ld1d\t%0.d, %5/z, [%2.d]
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ld1d\t%0.d, %5/z, [%2.d, #%1]
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ld1d\t%0.d, %5/z, [%1, %2.d]
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ld1d\t%0.d, %5/z, [%1, %2.d, lsl %p4]"
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ld1<Vesize>\t%0.d, %5/z, [%2.d]
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ld1<Vesize>\t%0.d, %5/z, [%2.d, #%1]
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ld1<Vesize>\t%0.d, %5/z, [%1, %2.d]
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ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]"
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)
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;; Likewise, but with the offset being sign-extended from 32 bits.
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(define_insn "*mask_gather_load<mode><v_int_equiv>_sxtw"
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[(set (match_operand:SVE_FULL_D 0 "register_operand" "=w, w")
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(unspec:SVE_FULL_D
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;; Likewise, but with the offset being extended from 32 bits.
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(define_insn_and_rewrite "*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked"
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[(set (match_operand:SVE_2 0 "register_operand" "=w, w")
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(unspec:SVE_2
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[(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
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(match_operand:DI 1 "register_operand" "rk, rk")
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(unspec:VNx2DI
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[(match_dup 5)
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[(match_operand 6)
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(ANY_EXTEND:VNx2DI
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(match_operand:VNx2SI 2 "register_operand" "w, w"))]
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UNSPEC_PRED_X)
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(match_operand:DI 3 "const_int_operand")
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(match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, i")
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(mem:BLK (scratch))]
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UNSPEC_LD1_GATHER))]
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"TARGET_SVE"
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"@
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ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, <su>xtw]
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ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, <su>xtw %p4]"
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"&& !CONSTANT_P (operands[6])"
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{
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operands[6] = CONSTM1_RTX (VNx2BImode);
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}
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)
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;; Likewise, but with the offset being truncated to 32 bits and then
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;; sign-extended.
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(define_insn_and_rewrite "*mask_gather_load<mode><v_int_container>_sxtw"
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[(set (match_operand:SVE_2 0 "register_operand" "=w, w")
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(unspec:SVE_2
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[(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
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(match_operand:DI 1 "register_operand" "rk, rk")
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(unspec:VNx2DI
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[(match_operand 6)
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(sign_extend:VNx2DI
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(truncate:VNx2SI
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(match_operand:VNx2DI 2 "register_operand" "w, w")))]
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UNSPEC_PRED_X)
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(match_operand:DI 3 "const_int_operand")
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(match_operand:DI 4 "aarch64_gather_scale_operand_d" "Ui1, i")
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(match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, i")
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(mem:BLK (scratch))]
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UNSPEC_LD1_GATHER))]
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"TARGET_SVE"
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"@
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ld1d\t%0.d, %5/z, [%1, %2.d, sxtw]
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ld1d\t%0.d, %5/z, [%1, %2.d, sxtw %p4]"
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ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw]
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ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw %p4]"
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"&& !CONSTANT_P (operands[6])"
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{
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operands[6] = CONSTM1_RTX (VNx2BImode);
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}
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)
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;; Likewise, but with the offset being zero-extended from 32 bits.
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(define_insn "*mask_gather_load<mode><v_int_equiv>_uxtw"
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[(set (match_operand:SVE_FULL_D 0 "register_operand" "=w, w")
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(unspec:SVE_FULL_D
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;; Likewise, but with the offset being truncated to 32 bits and then
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;; zero-extended.
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(define_insn "*mask_gather_load<mode><v_int_container>_uxtw"
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[(set (match_operand:SVE_2 0 "register_operand" "=w, w")
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(unspec:SVE_2
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[(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
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(match_operand:DI 1 "register_operand" "rk, rk")
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(and:VNx2DI
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(match_operand:VNx2DI 2 "register_operand" "w, w")
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(match_operand:VNx2DI 6 "aarch64_sve_uxtw_immediate"))
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(match_operand:DI 3 "const_int_operand")
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(match_operand:DI 4 "aarch64_gather_scale_operand_d" "Ui1, i")
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(match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, i")
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(mem:BLK (scratch))]
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UNSPEC_LD1_GATHER))]
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"TARGET_SVE"
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"@
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ld1d\t%0.d, %5/z, [%1, %2.d, uxtw]
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ld1d\t%0.d, %5/z, [%1, %2.d, uxtw %p4]"
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ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw]
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ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw %p4]"
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)
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;; -------------------------------------------------------------------------
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@ -364,6 +364,16 @@
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VNx4SI VNx2SI
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VNx2DI])
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;; SVE modes with 2 or 4 elements.
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(define_mode_iterator SVE_24 [VNx2QI VNx2HI VNx2HF VNx2SI VNx2SF VNx2DI VNx2DF
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VNx4QI VNx4HI VNx4HF VNx4SI VNx4SF])
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;; SVE modes with 2 elements.
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(define_mode_iterator SVE_2 [VNx2QI VNx2HI VNx2HF VNx2SI VNx2SF VNx2DI VNx2DF])
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;; SVE modes with 4 elements.
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(define_mode_iterator SVE_4 [VNx4QI VNx4HI VNx4HF VNx4SI VNx4SF])
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;; Modes involved in extending or truncating SVE data, for 8 elements per
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;; 128-bit block.
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(define_mode_iterator VNx8_NARROW [VNx8QI])
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@ -1113,6 +1123,31 @@
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(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
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(VNx2DI "vnx2df") (VNx2DF "vnx2df")])
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;; Maps full and partial vector modes of any element type to a full-vector
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;; integer mode with the same number of units.
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(define_mode_attr V_INT_CONTAINER [(VNx16QI "VNx16QI") (VNx8QI "VNx8HI")
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(VNx4QI "VNx4SI") (VNx2QI "VNx2DI")
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(VNx8HI "VNx8HI") (VNx4HI "VNx4SI")
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(VNx2HI "VNx2DI")
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(VNx4SI "VNx4SI") (VNx2SI "VNx2DI")
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(VNx2DI "VNx2DI")
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(VNx8HF "VNx8HI") (VNx4HF "VNx4SI")
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(VNx2HF "VNx2DI")
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(VNx4SF "VNx4SI") (VNx2SF "VNx2SI")
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(VNx2DF "VNx2DI")])
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;; Lower-case version of V_INT_CONTAINER.
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(define_mode_attr v_int_container [(VNx16QI "vnx16qi") (VNx8QI "vnx8hi")
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(VNx4QI "vnx4si") (VNx2QI "vnx2di")
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(VNx8HI "vnx8hi") (VNx4HI "vnx4si")
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(VNx2HI "vnx2di")
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(VNx4SI "vnx4si") (VNx2SI "vnx2di")
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(VNx2DI "vnx2di")
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(VNx8HF "vnx8hi") (VNx4HF "vnx4si")
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(VNx2HF "vnx2di")
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(VNx4SF "vnx4si") (VNx2SF "vnx2di")
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(VNx2DF "vnx2di")])
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;; Mode for vector conditional operations where the comparison has
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;; different type from the lhs.
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(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
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@ -1,3 +1,23 @@
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/gather_load_1.c (TEST_LOOP): Start at 0.
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(TEST_ALL): Add tests for 8-bit and 16-bit elements.
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* gcc.target/aarch64/sve/gather_load_2.c: Update accordingly.
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* gcc.target/aarch64/sve/gather_load_3.c (TEST_LOOP): Start at 0.
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(TEST_ALL): Add tests for 8-bit and 16-bit elements.
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* gcc.target/aarch64/sve/gather_load_4.c: Update accordingly.
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* gcc.target/aarch64/sve/gather_load_5.c (TEST_LOOP): Start at 0.
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(TEST_ALL): Add tests for 8-bit, 16-bit and 32-bit elements.
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* gcc.target/aarch64/sve/gather_load_6.c: Add
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--param aarch64-sve-compare-costs=0.
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(TEST_LOOP): Start at 0.
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* gcc.target/aarch64/sve/gather_load_7.c: Add
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--param aarch64-sve-compare-costs=0.
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* gcc.target/aarch64/sve/gather_load_8.c: New test.
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* gcc.target/aarch64/sve/gather_load_9.c: Likewise.
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* gcc.target/aarch64/sve/mask_gather_load_6.c: Add
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--param aarch64-sve-compare-costs=0.
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/mask_struct_load_1.c: Add
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@ -8,17 +8,20 @@
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#define INDEX64 int64_t
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#endif
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/* Invoked 18 times for each data size. */
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#define TEST_LOOP(DATA_TYPE, BITS) \
|
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void __attribute__ ((noinline, noclone)) \
|
||||
f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \
|
||||
INDEX##BITS *indices, int n) \
|
||||
{ \
|
||||
for (int i = 9; i < n; ++i) \
|
||||
for (int i = 0; i < n; ++i) \
|
||||
dest[i] += src[indices[i]]; \
|
||||
}
|
||||
|
||||
#define TEST_ALL(T) \
|
||||
T (int8_t, 32) \
|
||||
T (uint8_t, 32) \
|
||||
T (int16_t, 32) \
|
||||
T (uint16_t, 32) \
|
||||
T (int32_t, 32) \
|
||||
T (uint32_t, 32) \
|
||||
T (float, 32) \
|
||||
@ -28,5 +31,12 @@
|
||||
|
||||
TEST_ALL (TEST_LOOP)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw 1\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw 2\]\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x[0-9]+, z[0-9]+.d, lsl 3\]\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
|
||||
|
||||
@ -6,5 +6,12 @@
|
||||
|
||||
#include "gather_load_1.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw 1\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw 2\]\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x[0-9]+, z[0-9]+.d, lsl 3\]\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
|
||||
|
||||
@ -8,17 +8,20 @@
|
||||
#define INDEX64 int64_t
|
||||
#endif
|
||||
|
||||
/* Invoked 18 times for each data size. */
|
||||
#define TEST_LOOP(DATA_TYPE, BITS) \
|
||||
void __attribute__ ((noinline, noclone)) \
|
||||
f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \
|
||||
INDEX##BITS *indices, int n) \
|
||||
{ \
|
||||
for (int i = 9; i < n; ++i) \
|
||||
for (int i = 0; i < n; ++i) \
|
||||
dest[i] += *(DATA_TYPE *) ((char *) src + indices[i]); \
|
||||
}
|
||||
|
||||
#define TEST_ALL(T) \
|
||||
T (int8_t, 32) \
|
||||
T (uint8_t, 32) \
|
||||
T (int16_t, 32) \
|
||||
T (uint16_t, 32) \
|
||||
T (int32_t, 32) \
|
||||
T (uint32_t, 32) \
|
||||
T (float, 32) \
|
||||
@ -28,5 +31,12 @@
|
||||
|
||||
TEST_ALL (TEST_LOOP)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw\]\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x[0-9]+, z[0-9]+.d\]\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
|
||||
|
||||
@ -6,5 +6,12 @@
|
||||
|
||||
#include "gather_load_3.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw\]\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x[0-9]+, z[0-9]+.d\]\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
|
||||
|
||||
@ -3,21 +3,34 @@
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Invoked 18 times for each data size. */
|
||||
#define TEST_LOOP(DATA_TYPE) \
|
||||
void __attribute__ ((noinline, noclone)) \
|
||||
f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict *src, \
|
||||
int n) \
|
||||
{ \
|
||||
for (int i = 9; i < n; ++i) \
|
||||
for (int i = 0; i < n; ++i) \
|
||||
dest[i] += *src[i]; \
|
||||
}
|
||||
|
||||
#define TEST_ALL(T) \
|
||||
T (int8_t) \
|
||||
T (uint8_t) \
|
||||
T (int16_t) \
|
||||
T (uint16_t) \
|
||||
T (int32_t) \
|
||||
T (uint32_t) \
|
||||
T (int64_t) \
|
||||
T (uint64_t) \
|
||||
T (double)
|
||||
|
||||
TEST_ALL (TEST_LOOP)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d, p[0-7]/z, \[z[0-9]+.d\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d, p[0-7]/z, \[z[0-9]+.d\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d, p[0-7]/z, \[z[0-9]+.d\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[z[0-9]+.d\]\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.d,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.d,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.d,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -fwrapv --save-temps" } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -fwrapv --save-temps --param aarch64-sve-compare-costs=0" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
@ -8,13 +8,12 @@
|
||||
#define INDEX32 int32_t
|
||||
#endif
|
||||
|
||||
/* Invoked 18 times for each data size. */
|
||||
#define TEST_LOOP(DATA_TYPE, BITS) \
|
||||
void __attribute__ ((noinline, noclone)) \
|
||||
f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \
|
||||
INDEX##BITS *indices, INDEX##BITS mask, int n) \
|
||||
{ \
|
||||
for (int i = 9; i < n; ++i) \
|
||||
for (int i = 0; i < n; ++i) \
|
||||
dest[i] = src[(INDEX##BITS) (indices[i] | mask)]; \
|
||||
}
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize --save-temps" } */
|
||||
/* { dg-options "-O2 -ftree-vectorize --save-temps --param aarch64-sve-compare-costs=0" } */
|
||||
|
||||
#define INDEX16 uint16_t
|
||||
#define INDEX32 uint32_t
|
||||
|
||||
46
gcc/testsuite/gcc.target/aarch64/sve/gather_load_8.c
Normal file
46
gcc/testsuite/gcc.target/aarch64/sve/gather_load_8.c
Normal file
@ -0,0 +1,46 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -fwrapv --save-temps" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef INDEX32
|
||||
#define INDEX16 int16_t
|
||||
#define INDEX32 int32_t
|
||||
#endif
|
||||
|
||||
#define TEST_LOOP(DATA_TYPE, BITS) \
|
||||
void __attribute__ ((noinline, noclone)) \
|
||||
f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \
|
||||
INDEX##BITS *indices, INDEX##BITS mask, int n) \
|
||||
{ \
|
||||
for (int i = 0; i < n; ++i) \
|
||||
dest[i] = src[(INDEX##BITS) (indices[i] + mask)]; \
|
||||
}
|
||||
|
||||
#define TEST_ALL(T) \
|
||||
T (int8_t, 16) \
|
||||
T (uint8_t, 16) \
|
||||
T (int16_t, 16) \
|
||||
T (uint16_t, 16) \
|
||||
T (_Float16, 16) \
|
||||
T (int32_t, 16) \
|
||||
T (uint32_t, 16) \
|
||||
T (float, 16) \
|
||||
T (int64_t, 32) \
|
||||
T (uint64_t, 32) \
|
||||
T (double, 32)
|
||||
|
||||
TEST_ALL (TEST_LOOP)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw 1\]\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, sxtw 2\]\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x[0-9]+, z[0-9]+.d, sxtw 3\]\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsxt.\tz} 8 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsxth\tz[0-9]+\.s,} 8 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.s,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
|
||||
20
gcc/testsuite/gcc.target/aarch64/sve/gather_load_9.c
Normal file
20
gcc/testsuite/gcc.target/aarch64/sve/gather_load_9.c
Normal file
@ -0,0 +1,20 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -fwrapv --save-temps" } */
|
||||
|
||||
#define INDEX16 uint16_t
|
||||
#define INDEX32 uint32_t
|
||||
|
||||
#include "gather_load_8.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw\]\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw 1\]\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+.s, uxtw 2\]\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x[0-9]+, z[0-9]+.d, uxtw 3\]\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tuxt.\tz} 8 } } */
|
||||
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 8 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.s,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.s,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 3 } } */
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -ffast-math --save-temps" } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -ffast-math --save-temps --param aarch64-sve-compare-costs=0" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user