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arm.c (TARGET_MAX_ANCHOR_OFFSET): New.

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2008-08-28  Paul Brook  <paul@codesourcery.com>
	Mark Shinwell  <shinwell@codesourcery.com>
	Richard Earnshaw  <richard.earnshaw@arm.com>

	gcc/
	* config/arm/arm.c (TARGET_MAX_ANCHOR_OFFSET): New.
	(TARGET_MIN_ANCHOR_OFFSET): New.
	(arm_override_options): Set correct anchor ranges for Thumb-1
	and Thumb-2 if required.
	(legitimize_pic_address): Handle case involving a TLS symbol
	reference with an addend.
	(arm_optimization_options): Enable section anchors at -O1 and
	above.
	* config/arm/arm.h (OPTIMIZATION_OPTIONS): New.
	* config/arm/arm-protos.h (arm_optimization_options): New.


Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com>
Co-Authored-By: Richard Earnshaw <rearnsha@arm.com>

From-SVN: r139725
This commit is contained in:
Paul Brook 2008-08-28 18:03:51 +00:00 committed by Paul Brook
parent 8e1f752a26
commit f67358da6b
4 changed files with 69 additions and 0 deletions
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15
gcc/ChangeLog
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@ -1,3 +1,18 @@
2008-08-28 Paul Brook <paul@codesourcery.com>
Mark Shinwell <shinwell@codesourcery.com>
Richard Earnshaw <richard.earnshaw@arm.com>
* config/arm/arm.c (TARGET_MAX_ANCHOR_OFFSET): New.
(TARGET_MIN_ANCHOR_OFFSET): New.
(arm_override_options): Set correct anchor ranges for Thumb-1
and Thumb-2 if required.
(legitimize_pic_address): Handle case involving a TLS symbol
reference with an addend.
(arm_optimization_options): Enable section anchors at -O1 and
above.
* config/arm/arm.h (OPTIMIZATION_OPTIONS): New.
* config/arm/arm-protos.h (arm_optimization_options): New.
2008-08-28 Nick Clifton <nickc@redhat.com>
* config/stormy16/stormy16.h (IRA_COVER_CLASSES): Define.

1
gcc/config/arm/arm-protos.h
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@ -24,6 +24,7 @@
#define GCC_ARM_PROTOS_H
extern void arm_override_options (void);
extern void arm_optimization_options (int, int);
extern int use_return_insn (int, rtx);
extern int arm_regno_class (int);
extern void arm_load_pic_register (unsigned long);

50
gcc/config/arm/arm.c
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@ -367,6 +367,15 @@ static bool arm_allocate_stack_slots_for_args (void);
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
#undef TARGET_MAX_ANCHOR_OFFSET
#define TARGET_MAX_ANCHOR_OFFSET 4095
/* The minimum is set such that the total size of the block
for a particular anchor is -4088 + 1 + 4095 bytes, which is
divisible by eight, ensuring natural spacing of anchors. */
#undef TARGET_MIN_ANCHOR_OFFSET
#define TARGET_MIN_ANCHOR_OFFSET -4088
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE arm_issue_rate
@ -1267,6 +1276,27 @@ arm_override_options (void)
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
/* If we are not using the default (ARM mode) section anchor offset
ranges, then set the correct ranges now. */
if (TARGET_THUMB1)
{
/* Thumb-1 LDR instructions cannot have negative offsets.
Permissible positive offset ranges are 5-bit (for byte loads),
6-bit (for halfword loads), or 7-bit (for word loads).
Empirical results suggest a 7-bit anchor range gives the best
overall code size. */
targetm.min_anchor_offset = 0;
targetm.max_anchor_offset = 127;
}
else if (TARGET_THUMB2)
{
/* The minimum is set such that the total size of the block
for a particular anchor is 248 + 1 + 4095 bytes, which is
divisible by eight, ensuring natural spacing of anchors. */
targetm.min_anchor_offset = -248;
targetm.max_anchor_offset = 4095;
}
/* V5 code we generate is completely interworking capable, so we turn off
TARGET_INTERWORK here to avoid many tests later on. */
@ -3493,10 +3523,22 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
&& XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
return orig;
/* Handle the case where we have: const (UNSPEC_TLS). */
if (GET_CODE (XEXP (orig, 0)) == UNSPEC
&& XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
return orig;
/* Handle the case where we have:
const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a
CONST_INT. */
if (GET_CODE (XEXP (orig, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC
&& XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS)
{
gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT);
return orig;
}
if (reg == 0)
{
gcc_assert (can_create_pseudo_p ());
@ -19066,4 +19108,12 @@ arm_order_regs_for_local_alloc (void)
sizeof (thumb_core_reg_alloc_order));
}
/* Set default optimization options. */
void
arm_optimization_options (int level, int size ATTRIBUTE_UNUSED)
{
/* Enable section anchors by default at -O1 or higher. */
flag_section_anchors = (level > 0 ? 1 : 0);
}
#include "gt-arm.h"

3
gcc/config/arm/arm.h
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@ -427,6 +427,9 @@ extern int arm_arch_hwdiv;
#define OVERRIDE_OPTIONS arm_override_options ()
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
arm_optimization_options ((LEVEL), (SIZE))
/* Nonzero if PIC code requires explicit qualifiers to generate
PLT and GOT relocs rather than the assembler doing so implicitly.
Subtargets can override these if required. */