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aarch64: Prevent FPR register asms for +nofp

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+nofp disabled the automatic allocation of FPRs, but it didn't stop
users from explicitly putting register variables in FPRs.  We'd then
either report an ICE or generate unsupported instructions.

It's still possible (and deliberately redundant) to specify FPRs in
clobber lists.

gcc/
	* config/aarch64/aarch64.cc (aarch64_conditional_register_usage):
	Disallow use of FPRs in register asms for !TARGET_FLOAT.

gcc/testsuite/
	* gcc.target/aarch64/nofp_2.c: New test.
This commit is contained in:
Richard Sandiford 2022-09-07 10:52:03 +01:00
parent 0067ba052b
commit f58d5545d6
2 changed files with 20 additions and 0 deletions
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1
gcc/config/aarch64/aarch64.cc
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@ -19847,6 +19847,7 @@ aarch64_conditional_register_usage (void)
{
fixed_regs[i] = 1;
call_used_regs[i] = 1;
CLEAR_HARD_REG_BIT (operand_reg_set, i);
}
}
if (!TARGET_SVE)

19
gcc/testsuite/gcc.target/aarch64/nofp_2.c Normal file
View File

@ -0,0 +1,19 @@
/* { dg-options "" } */
#pragma GCC target "+nothing+nofp"
void
test (void)
{
register int q0 asm ("q0"); // { dg-error "not general enough" }
register int q1 asm ("q1"); // { dg-error "not general enough" }
asm volatile ("" : "=w" (q0));
q1 = q0;
asm volatile ("" :: "w" (q1));
}
void
ok (void)
{
asm volatile ("" ::: "q0");
}