mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-04-21 15:40:55 +08:00
Code Issues Packages Projects Releases Wiki Activity

rs6000: Optimize code generation of vec_reve [PR100868]

Browse Source 
gcc/
	PR target/100868
	* config/rs6000/altivec.md (altivec_vreve<mode>2 for VEC_K): Use
	xxbrq for v16qi, xxbrq + xxbrh for v8hi and xxbrq + xxbrw for v4si
	or v4sf when p9_vector is set.
	(altivec_vreve<mode>2 for VEC_64): Defined. Implemented by xxswapd.

gcc/testsuite/
	PR target/100868
	* gcc.target/powerpc/vec_reve_1.c: New test.
	* gcc.target/powerpc/vec_reve_2.c: Likewise.
This commit is contained in:
Haochen Gui 2021-11-17 16:16:02 +08:00
parent 1ddf11d364
commit f4eae6450e
3 changed files with 90 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
gcc/config/rs6000/altivec.md
View File

@ -3984,12 +3984,43 @@
DONE;
})
;; Vector reverse elements for V16QI V8HI V4SI V4SF
(define_expand "altivec_vreve<mode>2"
[(set (match_operand:VEC_A 0 "register_operand" "=v")
(unspec:VEC_A [(match_operand:VEC_A 1 "register_operand" "v")]
[(set (match_operand:VEC_K 0 "register_operand" "=v")
(unspec:VEC_K [(match_operand:VEC_K 1 "register_operand" "v")]
UNSPEC_VREVEV))]
"TARGET_ALTIVEC"
{
if (TARGET_P9_VECTOR)
{
if (<MODE>mode == V16QImode)
emit_insn (gen_p9_xxbrq_v16qi (operands[0], operands[1]));
else if (<MODE>mode == V8HImode)
{
rtx subreg1 = simplify_gen_subreg (V1TImode, operands[1],
<MODE>mode, 0);
rtx temp = gen_reg_rtx (V1TImode);
emit_insn (gen_p9_xxbrq_v1ti (temp, subreg1));
rtx subreg2 = simplify_gen_subreg (<MODE>mode, temp,
V1TImode, 0);
emit_insn (gen_p9_xxbrh_v8hi (operands[0], subreg2));
}
else /* V4SI and V4SF. */
{
rtx subreg1 = simplify_gen_subreg (V1TImode, operands[1],
<MODE>mode, 0);
rtx temp = gen_reg_rtx (V1TImode);
emit_insn (gen_p9_xxbrq_v1ti (temp, subreg1));
rtx subreg2 = simplify_gen_subreg (<MODE>mode, temp,
V1TImode, 0);
if (<MODE>mode == V4SImode)
emit_insn (gen_p9_xxbrw_v4si (operands[0], subreg2));
else
emit_insn (gen_p9_xxbrw_v4sf (operands[0], subreg2));
}
DONE;
}
int i, j, size, num_elements;
rtvec v = rtvec_alloc (16);
rtx mask = gen_reg_rtx (V16QImode);
@ -4008,6 +4039,17 @@
DONE;
})
;; Vector reverse elements for V2DI V2DF
(define_expand "altivec_vreve<mode>2"
[(set (match_operand:VEC_64 0 "register_operand" "=v")
(unspec:VEC_64 [(match_operand:VEC_64 1 "register_operand" "v")]
UNSPEC_VREVEV))]
"TARGET_ALTIVEC"
{
emit_insn (gen_xxswapd_<mode> (operands[0], operands[1]));
DONE;
})
;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
(define_insn "altivec_lvlx"

17
gcc/testsuite/gcc.target/powerpc/vec_reve_1.c Normal file
View File

@ -0,0 +1,17 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* { dg-options "-O2 -maltivec" } */
#include <altivec.h>
vector double foo1 (vector double a)
{
return vec_reve (a);
}
vector long long foo2 (vector long long a)
{
return vec_reve (a);
}
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 2 } } */

29
gcc/testsuite/gcc.target/powerpc/vec_reve_2.c Normal file
View File

@ -0,0 +1,29 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
#include <altivec.h>
vector int foo1 (vector int a)
{
return vec_reve (a);
}
vector float foo2 (vector float a)
{
return vec_reve (a);
}
vector short foo3 (vector short a)
{
return vec_reve (a);
}
vector char foo4 (vector char a)
{
return vec_reve (a);
}
/* { dg-final { scan-assembler-times {\mxxbrq\M} 4 } } */
/* { dg-final { scan-assembler-times {\mxxbrw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxbrh\M} 1 } } */