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re PR target/28946 (assembler shifts set the flag ZF, no need to re-test to zero)

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PR target/28946
        * config/i386/i386.md ("*ashldi3_cconly_rex64", "*ashlsi3_cconly",
        "*ashlhi3_cconly", "*ashlqi3_cconly", "*ashrdi3_one_bit_cconly_rex64",
        "*ashrdi3_cconly_rex64", "*ashrsi3_one_bit_cconly", "*ashrsi3_cconly",
        "*ashrhi3_one_bit_cconly", "*ashrhi3_cconly",
        "*ashrqi3_one_bit_cconly", "*ashrqi3_cconly",
        "*lshrdi3_cconly_one_bit_rex64", "*lshrdi3_cconly_rex64",
        "*lshrsi3_one_bit_cconly", "*lshrsi3_cconly",
        "*lshrhi3_one_bit_cconly", "*lshrhi3_cconly",
        "*lshrqi2_one_bit_cconly", "*lshrqi2_cconly": New patterns to
        implement only CC setting effects of shift instructions.

testsuite/ChangeLog:

       PR target/28946
       * gcc.target/i386/pr28946.c: New test.

From-SVN: r116756
This commit is contained in:
Uros Bizjak 2006-09-07 19:45:48 +02:00 committed by Uros Bizjak
parent d4a200d359
commit f42684d5c9
4 changed files with 395 additions and 0 deletions
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14
gcc/ChangeLog
View File

@ -1,3 +1,17 @@
2006-09-07 Uros Bizjak <uros@kss-loka.si>
PR target/28946
* config/i386/i386.md ("*ashldi3_cconly_rex64", "*ashlsi3_cconly",
"*ashlhi3_cconly", "*ashlqi3_cconly", "*ashrdi3_one_bit_cconly_rex64",
"*ashrdi3_cconly_rex64", "*ashrsi3_one_bit_cconly", "*ashrsi3_cconly",
"*ashrhi3_one_bit_cconly", "*ashrhi3_cconly",
"*ashrqi3_one_bit_cconly", "*ashrqi3_cconly",
"*lshrdi3_cconly_one_bit_rex64", "*lshrdi3_cconly_rex64",
"*lshrsi3_one_bit_cconly", "*lshrsi3_cconly",
"*lshrhi3_one_bit_cconly", "*lshrhi3_cconly",
"*lshrqi2_one_bit_cconly", "*lshrqi2_cconly": New patterns to
implement only CC setting effects of shift instructions.
2006-09-07 Martin Michlmayr <tbm@cyrius.com>
* doc/contrib.texi: Add myself.

361
gcc/config/i386/i386.md
View File

@ -10424,6 +10424,42 @@
(const_string "ishift")))
(set_attr "mode" "DI")])
(define_insn "*ashldi3_cconly_rex64"
[(set (reg FLAGS_REG)
(compare
(ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "immediate_operand" "e"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, DImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{q}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
return "sal{q}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_size))
return "sal{q}\t%0";
else
return "sal{q}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
]
(const_string "ishift")))
(set_attr "mode" "DI")])
(define_insn "*ashldi3_1"
[(set (match_operand:DI 0 "register_operand" "=&r,r")
(ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
@ -10705,6 +10741,42 @@
(const_string "ishift")))
(set_attr "mode" "SI")])
(define_insn "*ashlsi3_cconly"
[(set (reg FLAGS_REG)
(compare
(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{l}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
return "sal{l}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_size))
return "sal{l}\t%0";
else
return "sal{l}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
]
(const_string "ishift")))
(set_attr "mode" "SI")])
(define_insn "*ashlsi3_cmp_zext"
[(set (reg FLAGS_REG)
(compare
@ -10861,6 +10933,42 @@
(const_string "ishift")))
(set_attr "mode" "HI")])
(define_insn "*ashlhi3_cconly"
[(set (reg FLAGS_REG)
(compare
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{w}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
return "sal{w}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_size))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
]
(const_string "ishift")))
(set_attr "mode" "HI")])
(define_expand "ashlqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
@ -11019,6 +11127,42 @@
(const_string "ishift")))
(set_attr "mode" "QI")])
(define_insn "*ashlqi3_cconly"
[(set (reg FLAGS_REG)
(compare
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{b}\t{%0, %0|%0, %0}";
default:
if (REG_P (operands[2]))
return "sal{b}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_size))
return "sal{b}\t%0";
else
return "sal{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
(cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
(const_int 0))
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
]
(const_string "ishift")))
(set_attr "mode" "QI")])
;; See comment above `ashldi3' about how this works.
(define_expand "ashrti3"
@ -11162,6 +11306,20 @@
(const_string "2")
(const_string "*")))])
(define_insn "*ashrdi3_one_bit_cconly_rex64"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_SHIFT1 || optimize_size)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"sar{q}\t%0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
@ -11179,6 +11337,19 @@
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(define_insn "*ashrdi3_cconly_rex64"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_operand" "n"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"sar{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(define_insn "*ashrdi3_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
@ -11367,6 +11538,20 @@
(const_string "2")
(const_string "*")))])
(define_insn "*ashrsi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_SHIFT1 || optimize_size)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t%0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
(define_insn "*ashrsi3_one_bit_cmp_zext"
[(set (reg FLAGS_REG)
(compare
@ -11399,6 +11584,19 @@
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(define_insn "*ashrsi3_cconly"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(define_insn "*ashrsi3_cmp_zext"
[(set (reg FLAGS_REG)
(compare
@ -11468,6 +11666,20 @@
(const_string "2")
(const_string "*")))])
(define_insn "*ashrhi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_SHIFT1 || optimize_size)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"sar{w}\t%0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
@ -11485,6 +11697,19 @@
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
(define_insn "*ashrhi3_cconly"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"sar{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
(define_expand "ashrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
@ -11568,6 +11793,20 @@
(const_string "2")
(const_string "*")))])
(define_insn "*ashrqi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "I"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_SHIFT1 || optimize_size)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"sar{b}\t%0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
@ -11584,6 +11823,20 @@
"sar{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
(define_insn "*ashrqi3_cconly"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"sar{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
;; Logical shift instructions
@ -11697,6 +11950,20 @@
(const_string "2")
(const_string "*")))])
(define_insn "*lshrdi3_cconly_one_bit_rex64"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_SHIFT1 || optimize_size)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{q}\t%0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
@ -11714,6 +11981,19 @@
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(define_insn "*lshrdi3_cconly_rex64"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_operand" "e"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(define_insn "*lshrdi3_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
@ -11826,6 +12106,20 @@
(const_string "2")
(const_string "*")))])
(define_insn "*lshrsi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_SHIFT1 || optimize_size)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t%0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
(define_insn "*lshrsi3_cmp_one_bit_zext"
[(set (reg FLAGS_REG)
(compare
@ -11858,6 +12152,19 @@
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(define_insn "*lshrsi3_cconly"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(define_insn "*lshrsi3_cmp_zext"
[(set (reg FLAGS_REG)
(compare
@ -11927,6 +12234,20 @@
(const_string "2")
(const_string "*")))])
(define_insn "*lshrhi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_SHIFT1 || optimize_size)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{w}\t%0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
@ -11944,6 +12265,19 @@
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
(define_insn "*lshrhi3_cconly"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
(define_expand "lshrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
@ -12026,6 +12360,20 @@
(const_string "2")
(const_string "*")))])
(define_insn "*lshrqi2_one_bit_cconly"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_SHIFT1 || optimize_size)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"shr{b}\t%0"
[(set_attr "type" "ishift")
(set_attr "length" "2")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
@ -12042,6 +12390,19 @@
"shr{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
(define_insn "*lshrqi2_cconly"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"shr{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
;; Rotate instructions

5
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2006-09-07 Uros Bizjak <uros@kss-loka.si>
PR target/28946
* gcc.target/i386/pr28946.c: New test.
2006-09-07 Steven G. Kargl <kargls@comcast.net>
* gfortran.fortran-torture/compile/data_1.f90: Fix integer oveflow

15
gcc/testsuite/gcc.target/i386/pr28946.c Normal file
View File

@ -0,0 +1,15 @@
/* { dg-do compile } */
/* { dg-options "-O" } */
/* { dg-final { scan-assembler-not "test" } } */
int fct1 (void);
int fct2 (void);
int
fct (unsigned nb)
{
if ((nb >> 5) != 0)
return fct1 ();
else
return fct2 ();
}